[coreboot] GSoC project ideas

Peter Stuge peter at stuge.se
Fri Apr 6 06:16:53 CEST 2012

Paul Geraedts wrote:
> >> I will try to make my VHDL cores so they will be compatible with
> >> both types of boards. I plan to start with UART over USB support
> >> for the currently available Papilio boards.
> >
> > UART is stoneage idiotic useless. It's 2012, so please aim higher.
> Yet another opinion I guess;

It's a bit more than opinion.

> at the end of the day opinions should not matter.

What a nice way to say that you reject my input.

> >> Basically flashrom SPI access, POST code access and serial console
> >> access. This 'playground' should eventually give me enough insight
> >> in an optimal implementation when targeting future boards.
> >
> > Don't invent yet another packet protocol on top of a serial stream,
> > do this right the first time. You're planning on implementing three
> > different functions, and they really do need to use different
> > interfaces.
> Do not worry. No need for assumptions. I was not planning to.

SPI, port 80, and 16550 are the three functions you list, and which I
refer to. These are good features, that's not the point, the point is
that they are distinct features, so it makes sense to have them fall
out the other side of the FPGA as such.

> I will write a number of VHDL cores that plug in to a Wishbone
> interface that will also be connected to a USB controller.

Wishbone to some degree and USB for certain takes a lot of logic
space, and I think they're both way overkill for this simple FPGA
design. USB MAC core can make good sense if high speed is required,
but that's not the case for either of these functions.

Optimizing for design size allows cheaper and simpler implementation,
ideally the LPC slave can even be made to fit into a CPLD.

> In the first version that controller will be a (circuit-switched)
> UART over USB controller (switched either manually or by means of
> routing an extra GPIO pin of the FT2232D to the FPGA).

You overlook or ignore my earlier point. Use something more
structured than UART right from the start.

> Future boards is expected to contain improved USB hardware in several
> flavors ranging from a USB transceiver-only approach with USB stack in
> FPGA, to an FT232H in MPSSE mode, to a dedicated microprocesser with
> build-in USB and anything in between.

Right, I've talked with Jack about these things quite a bit.

> It should not matter what kind of hardware is used

It matters a lot for implementability, design size and thus
manufacturability based on possible usable parts.

> as long as it contains a similar Wishbone interface it will be
> transparant to the rest of the Wishbone cores.

I don't see the need for Wishbone in this design.

> > For the SPI flash emulator, suggest use IS61WV20488BLL-10TLI.
> The first prototype will not contain SRAM, but merely act as an SPI
> master mux. Due to its complexity, cost and GPIO pin count, I will
> only consider SRAM if absolutely necessary.

SRAM is trivial to interface, but it does need lots of pins! It
is in any case quite neccessary for the design to be useful for
development and testing; I believe the third usecase you listed

Please tell some more about your background?



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