[coreboot] GSoC project ideas

Paul Geraedts p.f.j.geraedts at gmail.com
Fri Apr 6 02:27:44 CEST 2012

On Thu Apr 5 06:31:36 CEST 2012, Peter Stuge wrote:

>> I will try to make my VHDL cores so they will be compatible with
>> both types of boards. I plan to start with UART over USB support
>> for the currently available Papilio boards.
> UART is stoneage idiotic useless. It's 2012, so please aim higher.

Yet another opinion I guess; at the end of the day opinions should not

>> Basically flashrom SPI access, POST code access and serial console
>> access. This 'playground' should eventually give me enough insight
>> in an optimal implementation when targeting future boards.
> Don't invent yet another packet protocol on top of a serial stream,
> do this right the first time. You're planning on implementing three
> different functions, and they really do need to use different
> interfaces.

Do not worry. No need for assumptions. I was not planning to.

I will write a number of VHDL cores that plug in to a Wishbone interface
that will also be connected to a USB controller. In the first version
that controller will be a (circuit-switched) UART over USB controller
(switched either manually or by means of routing an extra GPIO pin of
the FT2232D to the FPGA).

Future boards is expected to contain improved USB hardware in several
flavors ranging from a USB transceiver-only approach with USB stack in
FPGA, to an FT232H in MPSSE mode, to a dedicated microprocesser with
build-in USB and anything in between. It should not matter what kind of
hardware is used as long as it contains a similar Wishbone interface it
will be transparant to the rest of the Wishbone cores.

Thank you for the QiProg info.

> For the SPI flash emulator, suggest use IS61WV20488BLL-10TLI.

The first prototype will not contain SRAM, but merely act as an SPI
master mux. Due to its complexity, cost and GPIO pin count, I will
only consider SRAM if absolutely necessary.

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