[coreboot] Intel SCH CMC(Chipset Microcode) state machine binary?

[Alp Eren Köse]

2011/10/20 Svante Ekholm <svante.ekholm at crosscontrol.com>

> From what I’ve read from the Intel SCH specification, the CMC is a binary
> located at the top of the memory space at locations 0xFFFB0000, 0xFFFC0000,
> 0xFFFD0000 (default) or 0xFFFE0000. The location is determined by how the
> hardware sets two of the GPIO pins of the chipset. Of course these locations
> translate into ROM locations 0xB0000, 0xC0000, … etc, assuming a 1024 kB
> BIOS ROM. The binary is likely 0x10000 B or 64 kB in size. Copy the range
> 0xD0000-0xDFFFF from the vendor BIOS ROM to the coreboot ROM at the exact
> same range. In a 512 kB ROM, subtract 0x80000 from that range.
>
Hey thanks a lot!
Yep your suggestions really did help:)
I retrieved the CMC binary from the vendor BIOS file(which is read by
flashrom) and put it in coreboot. And now at least I get some serial
output:)
But unfortunately I needed a windoz machine to extract the CMC binary, you
can use the CBROM utility like this:
C:\> CBROM32_195.EXE vendor_bios.bin /TOPHOLE:FFFD0000 extract

And that will create a "TOP_HOLE.bin" file which you can place in coreboot,
but make will fail with:
make: *** No rule to make target `"cmc.bin"', needed by
`build/coreboot.pre1'. Stop.
For which you can find the solution at:
http://www.coreboot.org/pipermail/coreboot/2011-March/064246.html


>
> I’m attempting a Coreboot port to another Poulsbo board (the Kontron
> nanoETXexpress-SP) at the moment, so I’ve been following your thread with
> great interest. So far I’ve had about as much success as you, though.
>

So how far did you get? Do you get any output from the serial? If so where
does it hang?


P.S. Not all cbrom versions have the /TOPHOLE parameter, you can use the
32bit version 1.95.
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