[coreboot] Preview: SECC Pentium 2/3 users are gonna love this

Keith Hui buurin at gmail.com
Wed May 12 03:53:29 CEST 2010

See this boot log: http://coreboot.pastebin.com/rdmwwvha

I have done the 72oz steak ;-P that is porting the L2 enabling code
from coreboot v1 to current trunk, made much slimmer by being able to
put it post-raminit.

The CPU in question is a Pentium III 600MHz, Katmai core, 512KB cache.
Tell me if I am headed the right direction.

Patch to come soonish.


PS. Oh by the way...

[root at ojisan ~]# cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 7
model name      : Pentium III (Katmai)
stepping        : 3
cpu MHz         : 601.352
cache size      : 512 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca
cmov pse36 mmx fxsr sse up
bogomips        : 1202.70
clflush size    : 32
power management:

[root at ojisan ~]#

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