[coreboot] [commit] r5319 - trunk/src/arch/i386/include/arch

Patrick Georgi patrick at georgi-clan.de
Tue Mar 30 01:17:07 CEST 2010

Am 30.03.2010 01:05, schrieb Stefan Reinauer:
> I wonder, how can we completely create pirq_tables dynamically... Is it
> that hard?
> *                {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8},
> {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
>                 {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000},
> {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
>                 {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8},
> {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
>                 {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8},
> {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
>                 {0x00,(0x1d<<3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8},
> {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
> *
> How can we decide which interrupts to allow, i.e dcf8, dcd8, ...
> I saw some clean bios implementations that just created one PIRQ entry
> for every PCI device in the system... I think that should work for us, too.
> But how can we find out the mapping...
> If we could do this on ACPI boards only, that would be fine, ... ACPI
> knows the information, too, but in another format..
http://www.coreboot.org/GSoC#Board_config_infrastructure ;-)

Some of the entries have to be scrapped from chipset docs, I think. Once
we're on the PCI bus (which we don't automatically cover at all at this
time), it can be derived from the root bridge's irq routing.

So basically, we need to store some irq data, some chipset dependent,
some mainboard dependent. Is the device tree the right place for the
mainboard dependent parts?


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