[coreboot] [commit] r5320 - in trunk/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 advantech/pcm-5820 amd/db800 amd/dbm690t amd/mahogany amd/mahogany_fam10 amd/norwich amd/pistachio amd/ru...

repository service svn at coreboot.org
Tue Mar 30 00:08:01 CEST 2010


Author: stepan
Date: Tue Mar 30 00:08:01 2010
New Revision: 5320
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5320

Log:
This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run 
    awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
    mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c 
cut some holes into the source.

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>

Modified:
   trunk/src/mainboard/a-trend/atc-6220/romstage.c
   trunk/src/mainboard/a-trend/atc-6240/romstage.c
   trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c
   trunk/src/mainboard/advantech/pcm-5820/romstage.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/mainboard/amd/dbm690t/romstage.c
   trunk/src/mainboard/amd/mahogany/romstage.c
   trunk/src/mainboard/amd/mahogany_fam10/romstage.c
   trunk/src/mainboard/amd/norwich/romstage.c
   trunk/src/mainboard/amd/pistachio/romstage.c
   trunk/src/mainboard/amd/rumba/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
   trunk/src/mainboard/arima/hdama/romstage.c
   trunk/src/mainboard/artecgroup/dbe61/romstage.c
   trunk/src/mainboard/asi/mb_5blgp/romstage.c
   trunk/src/mainboard/asi/mb_5blmp/romstage.c
   trunk/src/mainboard/asus/a8n_e/romstage.c
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/asus/m2v-mx_se/romstage.c
   trunk/src/mainboard/asus/mew-am/romstage.c
   trunk/src/mainboard/asus/mew-vm/romstage.c
   trunk/src/mainboard/asus/p2b-d/romstage.c
   trunk/src/mainboard/asus/p2b-ds/romstage.c
   trunk/src/mainboard/asus/p2b-f/romstage.c
   trunk/src/mainboard/asus/p2b-ls/romstage.c
   trunk/src/mainboard/asus/p2b/romstage.c
   trunk/src/mainboard/asus/p3b-f/romstage.c
   trunk/src/mainboard/axus/tc320/romstage.c
   trunk/src/mainboard/azza/pt-6ibd/romstage.c
   trunk/src/mainboard/bcom/winnet100/romstage.c
   trunk/src/mainboard/bcom/winnetp680/romstage.c
   trunk/src/mainboard/biostar/m6tba/romstage.c
   trunk/src/mainboard/broadcom/blast/romstage.c
   trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
   trunk/src/mainboard/dell/s1850/romstage.c
   trunk/src/mainboard/digitallogic/adl855pc/romstage.c
   trunk/src/mainboard/digitallogic/msm586seg/romstage.c
   trunk/src/mainboard/digitallogic/msm800sev/romstage.c
   trunk/src/mainboard/eaglelion/5bcm/romstage.c
   trunk/src/mainboard/emulation/qemu-x86/romstage.c
   trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c
   trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
   trunk/src/mainboard/gigabyte/m57sli/romstage.c
   trunk/src/mainboard/hp/dl145_g3/romstage.c
   trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c
   trunk/src/mainboard/ibm/e325/romstage.c
   trunk/src/mainboard/ibm/e326/romstage.c
   trunk/src/mainboard/iei/juki-511p/romstage.c
   trunk/src/mainboard/iei/nova4899r/romstage.c
   trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
   trunk/src/mainboard/intel/d945gclf/romstage.c
   trunk/src/mainboard/intel/eagleheights/romstage.c
   trunk/src/mainboard/intel/jarrell/romstage.c
   trunk/src/mainboard/intel/mtarvon/romstage.c
   trunk/src/mainboard/intel/truxton/romstage.c
   trunk/src/mainboard/intel/xe7501devkit/romstage.c
   trunk/src/mainboard/iwill/dk8_htx/romstage.c
   trunk/src/mainboard/iwill/dk8s2/romstage.c
   trunk/src/mainboard/iwill/dk8x/romstage.c
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/mainboard/kontron/986lcd-m/romstage.c
   trunk/src/mainboard/kontron/kt690/romstage.c
   trunk/src/mainboard/lippert/frontrunner/romstage.c
   trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
   trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
   trunk/src/mainboard/mitac/6513wu/romstage.c
   trunk/src/mainboard/msi/ms6119/romstage.c
   trunk/src/mainboard/msi/ms6147/romstage.c
   trunk/src/mainboard/msi/ms6156/romstage.c
   trunk/src/mainboard/msi/ms6178/romstage.c
   trunk/src/mainboard/msi/ms7135/romstage.c
   trunk/src/mainboard/msi/ms7260/romstage.c
   trunk/src/mainboard/msi/ms9185/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/romstage.c
   trunk/src/mainboard/nec/powermate2000/romstage.c
   trunk/src/mainboard/newisys/khepri/romstage.c
   trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
   trunk/src/mainboard/olpc/btest/romstage.c
   trunk/src/mainboard/olpc/rev_a/romstage.c
   trunk/src/mainboard/pcengines/alix1c/romstage.c
   trunk/src/mainboard/rca/rm4100/romstage.c
   trunk/src/mainboard/roda/rk886ex/romstage.c
   trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
   trunk/src/mainboard/sunw/ultra40/romstage.c
   trunk/src/mainboard/supermicro/h8dme/romstage.c
   trunk/src/mainboard/supermicro/h8dmr/romstage.c
   trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
   trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
   trunk/src/mainboard/supermicro/x6dai_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
   trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
   trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
   trunk/src/mainboard/technexion/tim5690/romstage.c
   trunk/src/mainboard/technexion/tim8690/romstage.c
   trunk/src/mainboard/technologic/ts5300/romstage.c
   trunk/src/mainboard/televideo/tc7020/romstage.c
   trunk/src/mainboard/thomson/ip1000/romstage.c
   trunk/src/mainboard/tyan/s1846/romstage.c
   trunk/src/mainboard/tyan/s2735/romstage.c
   trunk/src/mainboard/tyan/s2850/romstage.c
   trunk/src/mainboard/tyan/s2875/romstage.c
   trunk/src/mainboard/tyan/s2880/romstage.c
   trunk/src/mainboard/tyan/s2881/romstage.c
   trunk/src/mainboard/tyan/s2882/romstage.c
   trunk/src/mainboard/tyan/s2885/romstage.c
   trunk/src/mainboard/tyan/s2891/romstage.c
   trunk/src/mainboard/tyan/s2892/romstage.c
   trunk/src/mainboard/tyan/s2895/romstage.c
   trunk/src/mainboard/tyan/s2912/romstage.c
   trunk/src/mainboard/tyan/s2912_fam10/romstage.c
   trunk/src/mainboard/tyan/s4880/romstage.c
   trunk/src/mainboard/tyan/s4882/romstage.c
   trunk/src/mainboard/via/epia-cn/romstage.c
   trunk/src/mainboard/via/epia-m/romstage.c
   trunk/src/mainboard/via/epia-m700/romstage.c
   trunk/src/mainboard/via/epia-n/romstage.c
   trunk/src/mainboard/via/epia/romstage.c
   trunk/src/mainboard/via/pc2500e/romstage.c
   trunk/src/mainboard/via/vt8454c/romstage.c
   trunk/src/mainboard/winent/pl6064/romstage.c

Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c
==============================================================================
--- trunk/src/mainboard/a-trend/atc-6220/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/a-trend/atc-6220/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c
==============================================================================
--- trunk/src/mainboard/a-trend/atc-6240/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/a-trend/atc-6240/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c
==============================================================================
--- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/advantech/pcm-5820/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -46,3 +43,4 @@
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/db800/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -87,7 +84,6 @@
        {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
 };
 
-
 static void msr_init(void)
 {
   int i;
@@ -133,3 +129,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+

Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -179,7 +176,6 @@
 	rs690_htinit();
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
-
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
 		soft_reset();
@@ -198,3 +194,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/mahogany/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -196,3 +193,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,15 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-
-
 //#define SYSTEM_TYPE 0	/* SERVER */
 #define SYSTEM_TYPE 1	/* DESKTOP */
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
@@ -71,7 +66,6 @@
 #define printk(BIOS_INFO, fmt, arg...)   do_printk(BIOS_INFO   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
-
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
@@ -86,17 +80,14 @@
 {
 }
 
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
-
 static int spd_read_byte(u32 device, u32 address)
 {
 	int result;
@@ -118,7 +109,6 @@
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
@@ -281,7 +271,6 @@
 //	ram_check(0x00200000, 0x00200000 + (640 * 1024));
 //	ram_check(0x40200000, 0x40200000 + (640 * 1024));
 
-
 //	die("After MCT init before CAR disabled.");
 
 	rs780_before_pci_init();
@@ -292,3 +281,4 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
+

Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/norwich/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,8 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -132,3 +130,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+

Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/pistachio/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -208,3 +205,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/rumba/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -118,7 +115,6 @@
 	/* put code in northbridge[init].c here */
 }
 
-
 static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
@@ -146,3 +142,4 @@
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
+

Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -32,7 +29,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-
 #if 0 
 static void post_code(uint8_t value) {
 #if 1
@@ -50,8 +46,6 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
-
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
@@ -142,7 +136,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -330,3 +323,4 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
+

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,15 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-#define ASSEMBLY 1
-
-
 #define SYSTEM_TYPE 0	/* SERVER */
 //#define SYSTEM_TYPE 1	/* DESKTOP */
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
@@ -71,7 +66,6 @@
 #endif
 #include "cpu/x86/bist.h"
 
-
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -87,12 +81,10 @@
 	outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
@@ -109,7 +101,6 @@
 	smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
-
 static int spd_read_byte(u32 device, u32 address)
 {
 	int result;
@@ -131,7 +122,6 @@
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -244,7 +234,6 @@
 	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
  #endif
 
-
 	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 	if (!warm_reset_detect(0)) {
 		print_info("...WARM RESET...\n\n\n");
@@ -254,7 +243,6 @@
 
 	post_code(0x3B);
 
-
 	/* FIXME:  Move this to chipset init.
 	enable cf9 for hard reset */
 	print_debug("enable_cf9_x()\n");
@@ -266,12 +254,10 @@
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	post_code(0x3D);
 
-
 	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
 	post_code(0x3E);
 
-
 	memreset_setup();
 	post_code(0x40);
 
@@ -281,7 +267,6 @@
 	raminit_amdmct(sysinfo);
 	post_code(0x41);
 
-
 /*
 	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
 	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
@@ -292,7 +277,6 @@
 //	ram_check(0x00200000, 0x00200000 + (640 * 1024));
 //	ram_check(0x40200000, 0x40200000 + (640 * 1024));
 
-
 //	die("After MCT init before CAR disabled.");
 
 	post_code(0x42);
@@ -300,6 +284,5 @@
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 
-
 }
 

Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/arima/hdama/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -169,3 +166,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -38,7 +35,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 
-
 #define POST_CODE(x) outb(x, 0x80)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
@@ -47,7 +43,6 @@
 #define DIMM0 0xA0
 #define DIMM1 0xA2
 
-
 static int spd_read_byte(unsigned device, unsigned address)
 {
 	int i;
@@ -182,3 +177,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
 	return;
 }
+

Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blgp/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asi/mb_5blgp/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
@@ -46,3 +43,4 @@
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blmp/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asi/mb_5blmp/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -55,3 +52,4 @@
 	/* Check whether RAM works. */
 	/* ram_check(0x00000000, 0x4000); */
 }
+

Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -21,9 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 /* Used by it8712f_enable_serial(). */
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 
@@ -195,3 +192,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -22,9 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
@@ -259,3 +256,4 @@
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -22,9 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
@@ -92,7 +89,6 @@
 
 #define K8_4RANK_DIMM_SUPPORT 1
 
-
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/raminit_f.c"
@@ -117,7 +113,6 @@
 	print_debug("done\r\n");
 }
 
-
 #include "cpu/amd/model_fxx/fidvid.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 
@@ -195,7 +190,6 @@
 
 	print_info("now booting... real_main\r\n");
 
-
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
@@ -234,7 +228,6 @@
 
 	}
 
-
 	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
 	/* allow LDT STOP asserts */
 	vt8237_sb_enable_fid_vid();
@@ -254,3 +247,4 @@
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/asus/mew-am/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/mew-am/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/mew-am/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -66,3 +63,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/mew-vm/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/mew-vm/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/mew-vm/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -68,3 +65,4 @@
 	/* Check RAM. */
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p2b-d/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-d/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p2b-d/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-ds/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p2b-ds/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p2b-f/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-f/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p2b-f/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b-ls/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p2b-ls/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -73,3 +70,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p2b/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p2b/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p2b/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/asus/p3b-f/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/p3b-f/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/asus/p3b-f/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/axus/tc320/romstage.c
==============================================================================
--- trunk/src/mainboard/axus/tc320/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/axus/tc320/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -47,3 +44,4 @@
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c
==============================================================================
--- trunk/src/mainboard/azza/pt-6ibd/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/azza/pt-6ibd/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/bcom/winnet100/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnet100/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/bcom/winnet100/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -55,3 +52,4 @@
 	/* Check whether RAM works. */
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -126,3 +123,4 @@
 
 	print_spew("Leaving romstage.c:main()\r\n");
 }
+

Modified: trunk/src/mainboard/biostar/m6tba/romstage.c
==============================================================================
--- trunk/src/mainboard/biostar/m6tba/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/biostar/m6tba/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/broadcom/blast/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
@@ -215,3 +212,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
==============================================================================
--- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -74,3 +71,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/dell/s1850/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -59,7 +56,6 @@
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  */
 
@@ -71,7 +67,6 @@
 #define ipmidata  0xca0
 #define ipmicsr  0xca4
 
-
 static inline void  ibfzero(void)
 {
 	while(inb(ipmicsr) &  (1<<IBF)) 
@@ -290,7 +285,6 @@
 	uart_init();
 	console_init();
 
-
 	/* stuff we seem to need */
 	pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 
@@ -371,3 +365,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #define ASM_CONSOLE_LOGLEVEL 8
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -46,8 +44,6 @@
 {
 }
 
-
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
         /* nothing to do */
@@ -83,7 +79,6 @@
         uart_init();
         console_init();
 
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 	
@@ -99,7 +94,6 @@
 	//        	dump_smbus_registers();
 #endif
 
-
 		memreset_setup();
 
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
@@ -142,3 +136,4 @@
 #endif
 */
 }
+

Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #define ASM_CONSOLE_LOGLEVEL 8
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -45,8 +43,6 @@
 
 typedef void (*lj)(void);
 
-
-
 struct mem_controller {
 	int i;
 };
@@ -59,8 +55,6 @@
 {
 }
 
-
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
         /* nothing to do */
@@ -90,7 +84,6 @@
   }
 }
 
-
 static inline void irqinit(void){
 	volatile unsigned char *cp;
 #if 0
@@ -186,15 +179,12 @@
 #endif
 }
 
-
-
 static void main(unsigned long bist)
 {
     volatile int i;
     for(i = 0; i < 100; i++)
       ;
 
-
         setupsc520();
 	irqinit();
         uart_init();
@@ -213,7 +203,6 @@
 	outb(0xee, 0x80);
 	print_err("loop forever ...\n");
 
-
 #if 0
 
 	/* clear memory 1meg */

Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -118,3 +115,4 @@
 	void done_cache_as_ram_main(void);
 	done_cache_as_ram_main();
 }
+

Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/eaglelion/5bcm/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -57,3 +54,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/emulation/qemu-x86/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -26,3 +24,4 @@
 	//print_pci_devices();
 	//dump_pci_devices();
 }
+

Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -21,9 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -147,7 +144,6 @@
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -212,7 +208,6 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 #if CONFIG_USBDEBUG_DIRECT
 	sis966_enable_usbdebug_direct(DBGP_DEFAULT);
 	early_usbdebug_direct_init();

Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -146,7 +143,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -167,7 +163,6 @@
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
@@ -226,7 +221,6 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 #if CONFIG_USBDEBUG_DIRECT
 	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
 	early_usbdebug_direct_init();

Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -25,9 +25,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -60,7 +57,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -79,7 +75,6 @@
 #include "superio/serverengines/pilot/pilot_early_init.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -139,7 +134,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
@@ -218,7 +212,6 @@
 		pc87417_enable_dev(RTC_DEV);
 	 }
 
-
 	 if (bist == 0) {
 		 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 	 }
@@ -232,7 +225,6 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 	console_init();
 //	setup_early_ipmi_serial();
 	pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV

Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -66,3 +63,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/ibm/e325/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -59,7 +57,6 @@
 	}
 }
 
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -92,7 +89,6 @@
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -167,3 +163,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/ibm/e326/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -59,7 +57,6 @@
 	}
 }
 
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -166,3 +163,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/iei/juki-511p/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iei/juki-511p/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -61,3 +58,4 @@
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/iei/nova4899r/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iei/nova4899r/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -56,3 +53,4 @@
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -135,3 +132,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+

Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,7 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-
 /* Configuration of the i945 driver */
 #define CHIPSET_I945GC 1
 #define CHANNEL_XOR_RANDOMIZATION 1
@@ -98,7 +97,6 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic

Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -20,8 +20,6 @@
  * MA 02110-1301 USA
  */
 
-
-
 #include <delay.h>
 
 #include <stdint.h>
@@ -236,3 +234,4 @@
 
 /* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"
+

Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/jarrell/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -53,7 +51,6 @@
 #include "lib/generic_sdram.c"
 #include "debug.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -150,3 +147,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,8 +18,6 @@
  *
  */
 
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -61,7 +59,6 @@
 #include "lib/generic_sdram.c"
 #include "../jarrell/debug.c"
 
-
 static void main(unsigned long bist)
 {
 	msr_t msr;
@@ -126,3 +123,4 @@
 
 	ram_check(0, 1024 * 1024);
 }
+

Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/truxton/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,8 +18,6 @@
  *
  */
 
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -113,3 +111,4 @@
 	ram_verify(0x00000000, 0x02000000);
 #endif
 }
+

Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/intel/xe7501devkit/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -44,7 +41,6 @@
 #include "northbridge/intel/e7501/reset_test.c"
 #include "lib/generic_sdram.c"
 
-
 // This function MUST appear last (ROMCC limitation)
 static void main(unsigned long bist)
 {
@@ -92,3 +88,4 @@
 	//		 if the following line is removed.
 	print_debug("SDRAM is up.\r\n");
 }
+

Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -39,7 +36,6 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
@@ -117,7 +113,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -193,7 +188,6 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-
 #if K8_SET_FIDVID == 1
 
         {
@@ -245,7 +239,6 @@
         init_timer(); // Need to use TMICT to synconize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-
 #if 0
         dump_pci_devices();
 #endif
@@ -253,3 +246,4 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
+

Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -39,7 +36,6 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
@@ -117,7 +113,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -193,7 +188,6 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-
 #if K8_SET_FIDVID == 1
 
         {
@@ -245,7 +239,6 @@
         init_timer(); // Need to use TMICT to synconize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-
 #if 0
         dump_pci_devices();
 #endif
@@ -253,3 +246,4 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
+

Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -116,7 +113,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -192,7 +188,6 @@
 	/* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-
 #if K8_SET_FIDVID == 1
 
         {
@@ -244,7 +239,6 @@
         init_timer(); // Need to use TMICT to synconize FID/VID
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-
 #if 0
         dump_pci_devices();
 #endif
@@ -252,3 +246,4 @@
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
+

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -128,3 +125,4 @@
 
 	print_spew("Leaving romstage.c:main()\r\n");
 }
+

Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,7 +19,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-
 /* Configuration of the i945 driver */
 #define CHIPSET_I945GM 1
 /* Usually system firmware turns off system memory clock signals to 
@@ -112,7 +111,6 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic

Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/kontron/kt690/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -182,7 +179,6 @@
 	rs690_htinit();
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
-
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
 		soft_reset();
@@ -201,3 +197,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -70,12 +67,10 @@
         __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
         __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
 
-
         __builtin_wrmsr(0x50002001, 0x27, 0x0);
         __builtin_wrmsr(0x4c002001, 0x1, 0x0);
 }
 
-
 static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {
@@ -104,7 +99,6 @@
 	outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
 	outb( 0x87, 0x4E);
 
-
    	outb(0x20, 0x4e);
 	temp = inb(0x4f);
 	print_debug_hex8(temp);
@@ -134,3 +128,4 @@
 //	ram_check(0x00000000, 640*1024);
 
 }
+

Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -21,9 +21,6 @@
 
 /* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
 
-#define ASSEMBLY 1
-
-
 #include <stdlib.h>
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -167,3 +164,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+

Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -21,9 +21,6 @@
 
 /* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */
 
-#define ASSEMBLY 1
-
-
 #include <stdlib.h>
 #include <stdint.h>
 #include <spd.h>
@@ -236,3 +233,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+

Modified: trunk/src/mainboard/mitac/6513wu/romstage.c
==============================================================================
--- trunk/src/mainboard/mitac/6513wu/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/mitac/6513wu/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -67,3 +64,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/msi/ms6119/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6119/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms6119/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/msi/ms6147/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6147/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms6147/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -78,3 +75,4 @@
 	ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */
 #endif
 }
+

Modified: trunk/src/mainboard/msi/ms6156/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6156/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms6156/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/msi/ms6178/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms6178/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms6178/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -67,3 +64,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms7135/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -22,9 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
 
 /* Used by raminit. */
@@ -199,3 +196,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms7260/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -20,9 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 // #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 // #define RAM_TIMING_DEBUG 1
 // #define DQS_TRAIN_DEBUG 1

Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms9185/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -23,9 +23,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -72,7 +69,6 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
@@ -112,8 +108,6 @@
 }
 #endif
 
-
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
         return smbus_read_byte(device, address);
@@ -145,7 +139,6 @@
 #define DIMM6 0x56
 #define DIMM7 0x57
 
-
 #include "cpu/amd/car/copy_and_run.c"
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -231,7 +224,6 @@
 
        bcm5785_early_setup();
 
-
 #if 0
        //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
         needs_reset = optimize_link_coherent_ht();
@@ -315,5 +307,5 @@
 
        post_cache_as_ram();
 
-
 }
+

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -22,9 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -136,7 +133,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -152,7 +148,6 @@
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 
-
 }
 
 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
@@ -243,3 +238,4 @@
        post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/nec/powermate2000/romstage.c
==============================================================================
--- trunk/src/mainboard/nec/powermate2000/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/nec/powermate2000/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -60,3 +57,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/newisys/khepri/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -3,7 +3,6 @@
  * Adapted by Stefan Reinauer <stepan at coresystems.de>
  * Additional (C) 2007 coresystems GmbH 
  */
-#define ASSEMBLY 1
 
  
 #include <stdint.h>
@@ -100,14 +99,12 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-
 #include "cpu/amd/car/copy_and_run.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -175,7 +172,6 @@
                	soft_reset();
        	}
 
-
         allow_all_aps_stop(bsp_apicid);
 
         nodes = get_nodes();
@@ -194,3 +190,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -146,7 +143,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -212,7 +208,6 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 #if CONFIG_USBDEBUG_DIRECT
 	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
 	early_usbdebug_direct_init();

Modified: trunk/src/mainboard/olpc/btest/romstage.c
==============================================================================
--- trunk/src/mainboard/olpc/btest/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/olpc/btest/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -38,9 +35,6 @@
         return r;
 }
 
-
-
-
 /* sdram parameters for OLPC:
 	row address = 13
 	col address = 9
@@ -192,3 +186,4 @@
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
+

Modified: trunk/src/mainboard/olpc/rev_a/romstage.c
==============================================================================
--- trunk/src/mainboard/olpc/rev_a/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/olpc/rev_a/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -38,9 +35,6 @@
         return r;
 }
 
-
-
-
 /* sdram parameters for OLPC:
 	row address = 13
 	col address = 9
@@ -192,3 +186,4 @@
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
+

Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <spd.h>
 #include <device/pci_def.h>
@@ -210,3 +207,4 @@
 	void done_cache_as_ram_main(void);
 	done_cache_as_ram_main();
 }
+

Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/rca/rm4100/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -133,3 +130,4 @@
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(64512 * 1024, 65536 * 1024); */
 }
+

Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -21,7 +21,6 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-
 /* Configuration of the i945 driver */
 #define CHIPSET_I945GM 1
 #define CHANNEL_XOR_RANDOMIZATION 1
@@ -79,7 +78,6 @@
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/intel/i945/raminit.h"
 #include "northbridge/intel/i945/raminit.c"
 #include "northbridge/intel/i945/errata.c"
@@ -102,7 +100,6 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic

Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
==============================================================================
--- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,7 +1,3 @@
-#define ASSEMBLY 1
-
-
-
 #define K8_ALLOCATE_IO_RANGE 1
 
 #define QRANK_DIMM_SUPPORT 1
@@ -78,7 +74,6 @@
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
@@ -111,11 +106,9 @@
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -217,3 +210,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -16,9 +16,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1

Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -77,7 +74,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -135,7 +131,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -70,7 +67,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -126,7 +122,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -194,7 +189,6 @@
         console_init();
   printk(BIOS_DEBUG, "\n");
 
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -293,7 +287,6 @@
 
 post_code(0x40);
 
-
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -71,7 +68,6 @@
 
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -130,7 +126,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -337,7 +332,6 @@
 
 post_code(0x40);
 
-
  printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
  post_code(0x41);

Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -24,7 +22,6 @@
 #include "northbridge/intel/e7525/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -55,7 +52,6 @@
 #include "northbridge/intel/e7525/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -139,3 +135,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -56,7 +53,6 @@
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -150,3 +146,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -56,7 +53,6 @@
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -151,3 +147,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -57,7 +54,6 @@
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -152,3 +148,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -25,7 +23,6 @@
 #include "northbridge/intel/e7520/memory_initialized.c"
 #include "cpu/x86/bist.h"
 
-
 #define SIO_GPIO_BASE 0x680
 #define SIO_XBUS_BASE 0x4880
 
@@ -57,7 +54,6 @@
 #include "northbridge/intel/e7520/raminit.c"
 #include "lib/generic_sdram.c"
 
-
 static void main(unsigned long bist)
 {
 	/*
@@ -152,3 +148,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -186,7 +183,6 @@
 	rs690_htinit();
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
-
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
 		soft_reset();
@@ -214,3 +210,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 #define K8_SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
@@ -111,7 +108,6 @@
 	struct cpuid_result cpuid1;
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
@@ -181,7 +177,6 @@
 	rs690_htinit();
 	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
-
 	if (needs_reset) {
 		print_info("ht reset -\r\n");
 		soft_reset();
@@ -200,3 +195,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/technologic/ts5300/romstage.c
==============================================================================
--- trunk/src/mainboard/technologic/ts5300/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/technologic/ts5300/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -4,8 +4,6 @@
  *   (c) 2006 coresystems GmbH
  */
 
-#define ASSEMBLY 1
-
 #define ASM_CONSOLE_LOGLEVEL 6
 #include <stdint.h>
 #include <device/pci_def.h>

Modified: trunk/src/mainboard/televideo/tc7020/romstage.c
==============================================================================
--- trunk/src/mainboard/televideo/tc7020/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/televideo/tc7020/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -55,3 +52,4 @@
 	/* Check whether RAM works. */
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <stdlib.h>
 #include <device/pci_def.h>
@@ -135,3 +132,4 @@
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(64512 * 1024, 65536 * 1024); */
 }
+

Modified: trunk/src/mainboard/tyan/s1846/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s1846/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s1846/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -71,3 +68,4 @@
 	sdram_enable();
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2735/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -72,12 +70,10 @@
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/intel/e7501/raminit.c"
 #include "northbridge/intel/e7501/reset_test.c"
 #include "lib/generic_sdram.c"
 
-
 #include "cpu/x86/car/copy_and_run.c"
 
 void amd64_main(unsigned long bist)
@@ -135,7 +131,6 @@
         dump_pci_device(PCI_DEV(0, 0, 0));
 #endif
 
-
 #if 1
         {
         	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
@@ -222,7 +217,7 @@
 	}
 #endif
 
-
 	print_debug("should not be here -\r\n");
 
 }
+

Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2850/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -157,3 +155,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2875/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -157,3 +155,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2880/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -15,7 +13,6 @@
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
 
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
@@ -159,3 +156,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2881/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
@@ -83,7 +80,6 @@
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -91,7 +87,6 @@
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-
 #include "cpu/amd/car/copy_and_run.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
@@ -186,3 +181,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2882/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -163,3 +161,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2885/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -91,7 +89,6 @@
 #endif
 #include "cpu/amd/dualcore/dualcore.c"
 
-
 #include "cpu/amd/car/copy_and_run.c"
 
 #include "cpu/amd/car/post_cache_as_ram.c"
@@ -165,7 +162,6 @@
                	soft_reset();
        	}
 
-
         allow_all_aps_stop(bsp_apicid);
 
         nodes = get_nodes();
@@ -184,3 +180,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2891/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1
 
@@ -203,3 +200,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2892/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define QRANK_DIMM_SUPPORT 1
 
 #if CONFIG_LOGICAL_CPUS==1
@@ -172,3 +169,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2895/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #define K8_ALLOCATE_IO_RANGE 1
 
 #define QRANK_DIMM_SUPPORT 1
@@ -217,3 +214,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2912/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define K8_ALLOCATE_IO_RANGE 1
@@ -144,7 +141,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-
 static void sio_setup(void)
 {
 
@@ -208,7 +204,6 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-
 #if CONFIG_USBDEBUG_DIRECT
 	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
 	early_usbdebug_direct_init();

Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0

Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s4880/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -208,3 +206,4 @@
 
 	post_cache_as_ram();
 }
+

Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/tyan/s4882/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,5 +1,3 @@
-#define ASSEMBLY 1
-
  
 #include <stdint.h>
 #include <string.h>
@@ -33,7 +31,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-
 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 static void memreset_setup(void)
@@ -199,3 +196,4 @@
 	post_cache_as_ram();
 
 }
+

Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/epia-cn/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -123,3 +120,4 @@
 
 	print_spew("Leaving romstage.c:main()\r\n");
 }
+

Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/epia-m/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -152,3 +149,4 @@
 	
 	print_spew("Leaving romstage.c:main()\r\n");
 }
+

Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/epia-m700/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -22,8 +22,6 @@
  * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch.
  */
 
-#define ASSEMBLY 1
-
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
@@ -814,3 +812,4 @@
 
 	print_debug("should not be here -\r\n");
 }
+

Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/epia-n/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -57,7 +54,6 @@
 	.channel0 = { 0x50 },
 };
 
-
 static void memreset_setup(void)
 {
 }
@@ -146,7 +142,6 @@
 	print_debug("Setup CPU Interface\r\n");
 	c3_cpu_setup(ctrl.d0f2);	
 
-
 	ddr_ram_setup();
 
 	if (bist == 0) {
@@ -158,3 +153,4 @@
 
 	print_spew("Leaving romstage.c:main()\r\n");
 }
+

Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/epia/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -126,3 +123,4 @@
 	}
 #endif
 }
+

Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/pc2500e/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -18,9 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -83,3 +80,4 @@
 
 	/* ram_check(0, 640 * 1024); */
 }
+

Modified: trunk/src/mainboard/via/vt8454c/romstage.c
==============================================================================
--- trunk/src/mainboard/via/vt8454c/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/via/vt8454c/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * MA 02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -132,3 +129,4 @@
 void amd64_main(unsigned long bist) {
 	main(bist);
 }
+

Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c	Tue Mar 30 00:05:26 2010	(r5319)
+++ trunk/src/mainboard/winent/pl6064/romstage.c	Tue Mar 30 00:08:01 2010	(r5320)
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -88,7 +85,6 @@
        {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
 };
 
-
 static void msr_init(void)
 {
   int i;
@@ -135,3 +131,4 @@
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
+




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