[coreboot] HELP: Porting i830 RAM init to 440BX, now it won't compile

[ron minnich]

On Tue, Mar 2, 2010 at 5:39 AM, Keith Hui <buurin at gmail.com> wrote:

> ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0
> ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0

fix this first. You really want your code to be warning-free.


>                 edosd |= 0x04;  // <<< ABORT!

did you try just edosd = edosd | 4;

just wondering if it's that simple.

>That's with the clock chip my board uses. Where should this code be
> placed?

depends on the chip I assume. Very, very early is my bet.

>
> The vendor BIOS placed the PIIX4E power management device base port at
> 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base port
> at 0x0F00. If I want to change the base port to match vendor BIOS, where
> should it be made?

Why? We've never seen a need to match these addresses up.

ron