[coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]

Hugh Greenberg hng at lanl.gov
Thu Oct 29 19:19:52 CET 2009

I was using gcc 4.3.  Without the patches, I still see a problem even 
with gcc 3.4.  With the patches and gcc 3.4, things seem to be better so 
far.  Thanks.

Hugh Greenberg

Ward Vandewege wrote:
> On Thu, Oct 22, 2009 at 09:16:14AM -0600, Myles Watson wrote:
>>> RAM end at 0x00200000 kB
>>> Lower RAM end at 0x00200000 kB
>>> Ram3
>>> Before starting clocks: Before memreset: cpu is pre_c0
>>> after first udelay
>> OK.  So the timer worked for the first udelay...
>> Does it only freeze when you have both CPUs enabled?  Have you tried it with
>> the no_smp patch again?  I'm grasping at straws.
> This is starting to sound like all the weirdness I was seeing when working on
> the h8dmr fam10 port a few months ago.
> Are you sure it hangs? I thought so at first as well, but it turned out that
> things were running extremely slowly when compiling with gcc 4.3 (32 bit). If
> I waited 5 minutes or so eventually the board would boot.
> Can you reproduce a hang when changing CONSOLE_LOGLEVEL ? In my case the
> board would just hang if I lowered the default loglevel to something less
> than 8.
> I never did figure out what was going on there. Ron thought perhaps there was
> a cache issue. I put a file in the tree with the issues I ran into
>   src/mainboard/supermicro/h8dmr_fam10/README
> I haven't been able to revisit yet as that particular box is in production.
> What toolchain are you using? 
> Thanks,
> Ward.

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