[coreboot] MTRR setup strategy

Stefan Reinauer stepan at coresystems.de
Sat Jan 24 20:46:20 CET 2009

ron minnich wrote:
>> We could achieve the same effect with a subtractive setup:
>> reg00: base=0x00000000 (   0MB), size=2048MB: write-back, count=1
>> reg01: base=0x7c000000 (1984MB), size=64MB: uncached, count=1
>> reg02: base=0x7bff0000 (1983MB), size=64kB: uncached, count=1
> it's a good point but I wonder: does VIA hardware have the ability to
> "hoist" this uncached memory to a reasonable alignment? That is what
> the SiS chipsets used to to. That would make this problem easier.

Hoisting will not be generally available, so even if one chipset can do
it, we need to solve the problem without it.
Overlaying MTRRs work fine for that matter. No hoisting needed.

The same problem we see above is on all UMA platforms (like the i945 or
the cx700) I've seen so far. I'd be surprised if it's different on the

> This sounds neat, we're going to need it. An interesting test for now
> would be to artificially limit memory size to that which can be
> described with 4 MTRRs. We would lose 200M or so that way but it would
> be helpful to see if that resolves the speed problem.
How would we lose 200M? The above example only requires 3 MTRRs?


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