[coreboot] v3 stage2 running from flash

[Carl-Daniel Hailfinger]

On 06.01.2009 17:55, ron minnich wrote:
> On Tue, Jan 6, 2009 at 2:59 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
>   
>> it was ridiculously simple. I added #defines for XIP_ROM_SIZE/BASE
>> in stage0.S like core2 has, and now it boots MUCH MUCH faster, until it gets
>> into phase6_init and does the MTRR init that I brought in from v2, after
>> that it slows back down. I'll send a patch to set that properly and to fix
>> it in core2 (currently hardcoded to a 1MB rom) soonish. Is the proper
>> solution to the MTRR problem to teach that mtrr_init() not to mess up the
>> caching MTRR, to set the caching back up after init, or just to not bother
>> with the late init?
>>     
>
> I think we need to get this right, but you could try skipping the late
> init to see what happens.
>
> I expect it will slow down once linux starts.
>   

The situation is a bit complicated.
As long as CAR is active, we don't want the cacheable area (CAR+ROM) to
be bigger than the cache to prevent cache evictions of CAR contents.
That means we can cache the boot block and maybe initram. In that
situation, having initram directly before the boot block is a huge speed
benefit.
Once CAR is no longer active, we immediately want to mark the whole ROM
and RAM as cacheable to speed up decompression.

Regards,
Carl-Daniel

-- 
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