[coreboot] v3 stage2 running from flash
rminnich at gmail.com
Tue Jan 6 17:55:51 CET 2009
On Tue, Jan 6, 2009 at 2:59 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> it was ridiculously simple. I added #defines for XIP_ROM_SIZE/BASE
> in stage0.S like core2 has, and now it boots MUCH MUCH faster, until it gets
> into phase6_init and does the MTRR init that I brought in from v2, after
> that it slows back down. I'll send a patch to set that properly and to fix
> it in core2 (currently hardcoded to a 1MB rom) soonish. Is the proper
> solution to the MTRR problem to teach that mtrr_init() not to mess up the
> caching MTRR, to set the caching back up after init, or just to not bother
> with the late init?
I think we need to get this right, but you could try skipping the late
init to see what happens.
I expect it will slow down once linux starts.
More information about the coreboot