[coreboot] Run PCI rom before PCI bus scan??

[Corey Osgood]

Another missed cc.

On Feb 7, 2008 5:46 PM, Corey Osgood <corey.osgood at gmail.com> wrote:

> On Feb 7, 2008 5:02 PM, <joe at smittys.pointclark.net> wrote:
>
> > Quoting Marc Karasek <Marc.Karasek at Sun.COM>:
> >
> > > Let me add me two cents..
> > >
> > > I have dealt with the Intel MACs in the past so let me dreg up some
> > > memorries...
> > >
> > > From what I recall,  you had a serial eeprom on the board that
> > > contained the init for the chip.  This was the 82545GM.
> > >
> > > The eeprom image was protected by a CRC and if the CRC failed it would
> > > not load the image.
> >
> > By CRC do you mean checksum? There is a checksum in the eeprom.
> >
> > > The device would also not be visible on the PCI
> > > Bus unless the eeprom was loaded.  I have attached the 82545 eeprom
> > > spec sheet (freely avail from Intel) maybe this will give you some
> > > insight.
> > >
> > > Intel has a program to read/update the paramters.  I never used it,
> > > mainly because I was on an embedded system running MIPS-Linux and they
> > > would only provide a x86 binary, no src code.   It took me a couple of
> > > iterations to get the eeprom right.  Maybe you can get the utility
> > from
> > > Intel and dump the eeprom. What I do not understand is why you would
> > be
> > > having problems with coreboot.  the only thing I can guess is the
> > > default eeprom is putting the MAC into a state that the BIOS must take
> > > it out of (maybe WoL).  Did you say you have the spec sheet for the
> > > part and it talks about the eeprom?
> > >
> > Marc I am able to read the eeprom in Linux with ethtool. Wol is
> > enabled. This is a 82562ET chipset (same family). Corey, I am pretty
> > sure that atmel chip is the eeprom. Again, here is what I think needs
> > to be done:
> >
> > OK, here is what I have picked up reading, reading, and more reading:
> > 1. When the system is powered on "At this point, the LAN
> > controller is in the D0u state"
> >
> > 2. The "Platform LAN Connect component" is actually a command script
> > (probibly a rom written in assembly) runs and sets up the CSR register
> > (I could setup a script in the mainboard directory and run from auto.c).
> >
> > 3. At this point it goes into a DOa state.
> >
> > 3. The "Platform LAN Connect component" hands it over to the bios
> > (coreboot) to setup "Memory, or I/O Base Registers in the PCI
> > Configuration space"
> >
> > 4. nic is setup and ready to go!
> >
> > What do you think?
> >
> > The only thing I am not sure of is how to read/write to the CSR
> > register???
> >
> >
> > Thanks - Joe
> >
>
>
>
> I apologize if this seems disorganized, I'm trying to work it out:
>
> 1: set up csr memory/io base in the nic. ami bios uses 0xff7ff000 for mem
> base, and 0xdc01 as io base, these values should work to test with.
> Datasheet contradicts itself, says bits 3:0 of the mem base registers are
> all hardwired to 0, then gives a default value of 0x8.
>
> 2: write 0x3 to register 0xe (in IO space?) to enable the rom and clock.
> if this is io space, the write is just outb(val, (NIC_IO_BASE + reg)). There
> are reserved registers, so be sure to do a read-modify-write.
>
> 3: reset the lan controller? write 1 to bit 3 of 0x1c. Wait 1ms
> afterwards.
>
> Good luck, hope this helps
> -Corey
>
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