[coreboot] v3 and partially memory-mapped ROMs

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Mon Aug 4 01:59:46 CEST 2008


this problem has been mentioned by me in the past, but I'd like to
remind people of it now that we're working on a M57SLI port to v3.

The LAR code and lots of other places can't cope with partially mapped
ROMs. There are two options:
- Rewrite the LAR+string code to use accessor functions: Ugly, makes the
code completely unreadable, severe performance penalty, people will wash
their eyes with bleach after reading it, makes sure the person writing
the code will be the only one to ever understand it.
- Require the bootblock and initram to be in the mapped area and mirror
the complete ROM into RAM after RAM is enabled: No overhead except for
stage2 and payloads, existing LAR+string code can be used after a small
audit, faster decompression for unmapped areas (up to a factor of two
for the M57SLI rev2, up to a factor of four for other chipsets),
needless copying of all unused (fallback, alternative payload) ROM areas.



More information about the coreboot mailing list