[LinuxBIOS] SPI flash-chips

Anton anton.borisov at gmail.com
Mon Mar 12 18:47:00 CET 2007


On Mon, 12 Mar 2007 13:30:23 -0400
Richard Smith <smithbone at gmail.com> wrote:

> Where is the LPC <-> SPI being done?  Can the northbridge do both?  If 
> there is a additional chip (say like an EC) that does the LPC to SPI 
> conversion then there might be a way to put that device into recovery 
> mode where you can download new bits into the SPI flash.

	I can't say for sure - no schematic available. Yet.
> 
> Otherwise you just have to remove the SPI part device and add a SOIC to 
> DIP socket and use a DIP part.  SOIC sockets are a pain in the ass the use.
> 
> Or like Carl suggests. Lift the enable pin and wire up your own select 
> system.  Essentially the same as PLCC only less pins.

	I've been thinking about the same solution as Carl-Daniel
suggested. Just to verify once again, that it would work as planned.

Thanks.




More information about the coreboot mailing list