V1 PIRQ table

ron minnich rminnich at lanl.gov
Wed Jul 14 14:16:01 CEST 2004

On Wed, 14 Jul 2004, Richard Smith wrote:

> I don't uderstand how this will work.  In order for those writes to go 
> to RAM you have to have your shadowing control set up properly.  On my 
> chipset at this stage both reads and writes to areas such as f0000 are 
> forwarded to PCI so the write will fail.

What I do in this case is set CONFIG_COMPRESSED to 0, since if you 
don't have shadow ram working you're toast.


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