[coreboot-gerrit] Change in coreboot[master]: soc/cavium/cn81xx/spi: Add function to return SPI clock

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28789 )

Change subject: soc/cavium/cn81xx/spi: Add function to return SPI clock
......................................................................

soc/cavium/cn81xx/spi: Add function to return SPI clock

Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
Reviewed-on: https://review.coreboot.org/28789
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
---
M src/soc/cavium/cn81xx/include/soc/spi.h
M src/soc/cavium/cn81xx/spi.c
2 files changed, 22 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Philipp Deppenwiese: Looks good to me, approved



diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h
index bb69daa..33f0f29 100644
--- a/src/soc/cavium/cn81xx/include/soc/spi.h
+++ b/src/soc/cavium/cn81xx/include/soc/spi.h
@@ -29,6 +29,7 @@
 		   const size_t speed_hz,
 		   const size_t idle_low,
 		   const size_t idle_cycles);
+uint64_t spi_get_clock(const size_t bus);
 void spi_set_lsbmsb(const size_t bus, const size_t lsb_first);
 void spi_init_custom(const size_t bus,
 		     const size_t speed_hz,
diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c
index 5a5865e..6527f22 100644
--- a/src/soc/cavium/cn81xx/spi.c
+++ b/src/soc/cavium/cn81xx/spi.c
@@ -218,6 +218,27 @@
 }
 
 /**
+ * Get current SPI clock frequency in Hz.
+ *
+ * @param bus                 The SPI bus to operate on
+ */
+uint64_t spi_get_clock(const size_t bus)
+{
+	union cavium_spi_cfg cfg;
+
+	assert(bus < ARRAY_SIZE(cavium_spi_slaves));
+	if (bus >= ARRAY_SIZE(cavium_spi_slaves))
+		return 0;
+
+	struct cavium_spi *regs = cavium_spi_slaves[bus].regs;
+	const uint64_t sclk = thunderx_get_io_clock();
+
+	cfg.u = read64(&regs->cfg);
+
+	return (sclk / (2ULL * cfg.s.clkdiv));
+}
+
+/**
  * Set SPI LSB/MSB first.
  *
  * @param bus                 The SPI bus to operate on

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8
Gerrit-Change-Number: 28789
Gerrit-PatchSet: 2
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: David Hendricks <david.hendricks at gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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