[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
Subrata Banik (Code Review)
gerrit at coreboot.org
Fri Sep 28 17:15:04 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28792
Change subject: soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
......................................................................
soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/include/soc/itss.h
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28792/1
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 34a2fe0..fadd5f8 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -22,9 +22,11 @@
#include <fsp/util.h>
#include <intelblocks/acpi.h>
#include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
@@ -134,11 +136,18 @@
void soc_init_pre_device(void *chip_info)
{
+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a
+ * default policy that doesn't honor boards' requirements. */
+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
+
+ /* Restore GPIO IRQ polarities back to previous settings. */
+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
}
static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h
index 06dcc2e..0d8b2ca 100644
--- a/src/soc/intel/cannonlake/include/soc/itss.h
+++ b/src/soc/intel/cannonlake/include/soc/itss.h
@@ -16,6 +16,9 @@
#ifndef SOC_INTEL_CNL_ITSS_H
#define SOC_INTEL_CNL_ITSS_H
+#define GPIO_IRQ_START 50
+#define GPIO_IRQ_END ITSS_MAX_IRQ
+
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Gerrit-Change-Number: 28792
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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