<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28792">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers<br><br>This patch save and restore ITSS IPCx register before and after<br>FSP-S call.<br><br>Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/include/soc/itss.h<br>2 files changed, 12 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28792/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 34a2fe0..fadd5f8 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -22,9 +22,11 @@</span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/acpi.h></span><br><span> #include <intelblocks/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/itss.h></span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/intel/common/vbt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/itss.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/ramstage.h></span><br><span> #include <string.h></span><br><span>@@ -134,11 +136,18 @@</span><br><span> </span><br><span> void soc_init_pre_device(void *chip_info)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a</span><br><span style="color: hsl(120, 100%, 40%);">+ * default policy that doesn't honor boards' requirements. */</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Perform silicon specific init. */</span><br><span> fsp_silicon_init(romstage_handoff_is_resume());</span><br><span> </span><br><span> /* Display FIRMWARE_VERSION_INFO_HOB */</span><br><span> fsp_display_fvi_version_hob();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Restore GPIO IRQ polarities back to previous settings. */</span><br><span style="color: hsl(120, 100%, 40%);">+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);</span><br><span> }</span><br><span> </span><br><span> static void pci_domain_set_resources(struct device *dev)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/itss.h b/src/soc/intel/cannonlake/include/soc/itss.h</span><br><span>index 06dcc2e..0d8b2ca 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/itss.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/itss.h</span><br><span>@@ -16,6 +16,9 @@</span><br><span> #ifndef SOC_INTEL_CNL_ITSS_H</span><br><span> #define SOC_INTEL_CNL_ITSS_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ_START 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_IRQ_END ITSS_MAX_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define ITSS_MAX_IRQ 119</span><br><span> #define IRQS_PER_IPC 32</span><br><span> #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28792">change 28792</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28792"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 </div>
<div style="display:none"> Gerrit-Change-Number: 28792 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>