[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix ACPI FADT table generation

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/28755


Change subject: soc/intel/cannonlake: Fix ACPI FADT table generation
......................................................................

soc/intel/cannonlake: Fix ACPI FADT table generation

The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set.  This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.

Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
M src/soc/intel/cannonlake/acpi.c
1 file changed, 11 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28755/1

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 155756c..a27055a 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -176,19 +176,18 @@
 	const struct device *dev = PCH_DEV_LPC;
 	const struct soc_intel_cannonlake_config *config = dev->chip_info;
 
-	if (config->PmTimerDisabled != 0)
-		return;
+	if (!config->PmTimerDisabled) {
+		fadt->pm_tmr_blk = pmbase + PM1_TMR;
+		fadt->pm_tmr_len = 4;
+		fadt->x_pm_tmr_blk.space_id = 1;
+		fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+		fadt->x_pm_tmr_blk.bit_offset = 0;
+		fadt->x_pm_tmr_blk.resv = 0;
+		fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+		fadt->x_pm_tmr_blk.addrh = 0x0;
+	}
 
-	fadt->pm_tmr_blk = pmbase + PM1_TMR;
-	fadt->pm_tmr_len = 4;
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	if(config->s0ix_enable)
+	if (config->s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 uint32_t soc_read_sci_irq_select(void)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Gerrit-Change-Number: 28755
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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