[coreboot-gerrit] Change in coreboot[master]: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28745


Change subject: nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs
......................................................................

nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs

Also correct IA-32 MSRs names

Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/intel/nehalem/early_init.c
1 file changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28745/1

diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 0a9b408..1ebb2a5 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -110,11 +110,11 @@
 		m.lo = (m.lo & ~0xff) | reg8;
 		wrmsr(IA32_PERF_CTL, m);
 
-		m = rdmsr(MSR_IA32_MISC_ENABLES);
+		m = rdmsr(IA32_MISC_ENABLE);
 		m.hi &= ~0x00000040;
 		m.lo |= 0x10000;
 
-		wrmsr(MSR_IA32_MISC_ENABLES, m);
+		wrmsr(IA32_MISC_ENABLE, m);
 	}
 
 	m = rdmsr(MSR_FSB_CLOCK_VCC);
@@ -124,9 +124,9 @@
 	m.lo = (m.lo & ~0xff) | reg8;
 	wrmsr(IA32_PERF_CTL, m);
 
-	m = rdmsr(MSR_IA32_MISC_ENABLES);
+	m = rdmsr(IA32_MISC_ENABLE);
 	m.lo |= 0x10000;
-	wrmsr(MSR_IA32_MISC_ENABLES, m);
+	wrmsr(IA32_MISC_ENABLE, m);
 }
 
 void nehalem_early_initialization(int chipset_type)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612
Gerrit-Change-Number: 28745
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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