<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28745">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/nehalem: Use "cpu/x86/msr.h" for common IA-32 MSRs<br><br>Also correct IA-32 MSRs names<br><br>Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/intel/nehalem/early_init.c<br>1 file changed, 4 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28745/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c</span><br><span>index 0a9b408..1ebb2a5 100644</span><br><span>--- a/src/northbridge/intel/nehalem/early_init.c</span><br><span>+++ b/src/northbridge/intel/nehalem/early_init.c</span><br><span>@@ -110,11 +110,11 @@</span><br><span>            m.lo = (m.lo & ~0xff) | reg8;</span><br><span>            wrmsr(IA32_PERF_CTL, m);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-            m = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+             m = rdmsr(IA32_MISC_ENABLE);</span><br><span>                 m.hi &= ~0x00000040;</span><br><span>             m.lo |= 0x10000;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-            wrmsr(MSR_IA32_MISC_ENABLES, m);</span><br><span style="color: hsl(120, 100%, 40%);">+              wrmsr(IA32_MISC_ENABLE, m);</span><br><span>  }</span><br><span> </span><br><span>        m = rdmsr(MSR_FSB_CLOCK_VCC);</span><br><span>@@ -124,9 +124,9 @@</span><br><span>  m.lo = (m.lo & ~0xff) | reg8;</span><br><span>    wrmsr(IA32_PERF_CTL, m);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    m = rdmsr(MSR_IA32_MISC_ENABLES);</span><br><span style="color: hsl(120, 100%, 40%);">+     m = rdmsr(IA32_MISC_ENABLE);</span><br><span>         m.lo |= 0x10000;</span><br><span style="color: hsl(0, 100%, 40%);">-        wrmsr(MSR_IA32_MISC_ENABLES, m);</span><br><span style="color: hsl(120, 100%, 40%);">+      wrmsr(IA32_MISC_ENABLE, m);</span><br><span> }</span><br><span> </span><br><span> void nehalem_early_initialization(int chipset_type)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28745">change 28745</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28745"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I45b52bbeb2f81f4c064bba92286c3f61daba9612 </div>
<div style="display:none"> Gerrit-Change-Number: 28745 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>