[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Don't use device_t
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Sep 21 16:13:05 CEST 2018
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28657 )
Change subject: sb/intel/bd82x6x: Don't use device_t
......................................................................
sb/intel/bd82x6x: Don't use device_t
Use of device_t is deprecated.
Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
Reviewed-on: https://review.coreboot.org/28657
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pch.h
4 files changed, 20 insertions(+), 20 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jonathan Neuschäfer: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 70ba301..da1c7e4 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -115,7 +115,7 @@
}
#ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -543,7 +543,7 @@
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -610,7 +610,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -640,7 +640,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -687,14 +687,14 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
me_bios_path path = intel_me_path(dev);
@@ -736,7 +736,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 9011787..1a59dc4 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -117,7 +117,7 @@
}
#ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -523,7 +523,7 @@
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -597,7 +597,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -627,7 +627,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -674,14 +674,14 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
me_bios_path path = intel_me_path(dev);
me_bios_payload mbp_data;
@@ -739,7 +739,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 79cf6bf..00265d0 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -208,9 +208,9 @@
}
/* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(struct device *dev)
{
- device_t port;
+ struct device *port;
int port_func;
int dev_func = PCI_FUNC(dev->path.pci.devfn);
@@ -258,7 +258,7 @@
static void pch_pcie_devicetree_update(
struct southbridge_intel_bd82x6x_config *config)
{
- device_t dev;
+ struct device *dev;
/*
* hotplug map should also be updated along with their
@@ -312,7 +312,7 @@
}
/* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
u32 reg32;
@@ -422,7 +422,7 @@
}
}
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
{
u32 reg32;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 65aac55..66f5727 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -64,7 +64,7 @@
#if !defined(__PRE_RAM__)
#if !defined(__SIMPLE_DEVICE__)
#include "chip.h"
-void pch_enable(device_t dev);
+void pch_enable(struct device *dev);
#endif
int pch_silicon_revision(void);
int pch_silicon_type(void);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Gerrit-Change-Number: 28657
Gerrit-PatchSet: 8
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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