<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/28657">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Jonathan Neuschäfer: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x: Don't use device_t<br><br>Use of device_t is deprecated.<br><br>Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>Reviewed-on: https://review.coreboot.org/28657<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/bd82x6x/pch.c<br>M src/southbridge/intel/bd82x6x/pch.h<br>4 files changed, 20 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c</span><br><span>index 70ba301..da1c7e4 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me.c</span><br><span>@@ -115,7 +115,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifndef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span> u32 dword = pci_read_config32(dev, offset);</span><br><span> memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -543,7 +543,7 @@</span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span> struct me_hfs hfs;</span><br><span>@@ -610,7 +610,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct mei_csr host;</span><br><span>@@ -640,7 +640,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span> struct me_heres status;</span><br><span> u32 extend[8] = {0};</span><br><span>@@ -687,14 +687,14 @@</span><br><span> }</span><br><span> </span><br><span> /* Hide the ME virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_hide(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_hide(struct device *dev)</span><br><span> {</span><br><span> dev->enabled = 0;</span><br><span> pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = intel_me_path(dev);</span><br><span> </span><br><span>@@ -736,7 +736,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>index 9011787..1a59dc4 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>@@ -117,7 +117,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifndef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span> u32 dword = pci_read_config32(dev, offset);</span><br><span> memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -523,7 +523,7 @@</span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span> struct me_hfs hfs;</span><br><span>@@ -597,7 +597,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct mei_csr host;</span><br><span>@@ -627,7 +627,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span> struct me_heres status;</span><br><span> u32 extend[8] = {0};</span><br><span>@@ -674,14 +674,14 @@</span><br><span> }</span><br><span> </span><br><span> /* Hide the ME virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_hide(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_hide(struct device *dev)</span><br><span> {</span><br><span> dev->enabled = 0;</span><br><span> pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = intel_me_path(dev);</span><br><span> me_bios_payload mbp_data;</span><br><span>@@ -739,7 +739,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>index 79cf6bf..00265d0 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>@@ -208,9 +208,9 @@</span><br><span> }</span><br><span> </span><br><span> /* Check if any port in set X to X+3 is enabled */</span><br><span style="color: hsl(0, 100%, 40%);">-static int pch_pcie_check_set_enabled(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_pcie_check_set_enabled(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t port;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *port;</span><br><span> int port_func;</span><br><span> int dev_func = PCI_FUNC(dev->path.pci.devfn);</span><br><span> </span><br><span>@@ -258,7 +258,7 @@</span><br><span> static void pch_pcie_devicetree_update(</span><br><span> struct southbridge_intel_bd82x6x_config *config)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> </span><br><span> /*</span><br><span> * hotplug map should also be updated along with their</span><br><span>@@ -312,7 +312,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Special handling for PCIe Root Port devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span> struct southbridge_intel_bd82x6x_config *config = dev->chip_info;</span><br><span> u32 reg32;</span><br><span>@@ -422,7 +422,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>index 65aac55..66f5727 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.h</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.h</span><br><span>@@ -64,7 +64,7 @@</span><br><span> #if !defined(__PRE_RAM__)</span><br><span> #if !defined(__SIMPLE_DEVICE__)</span><br><span> #include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev);</span><br><span> #endif</span><br><span> int pch_silicon_revision(void);</span><br><span> int pch_silicon_type(void);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28657">change 28657</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 </div>
<div style="display:none"> Gerrit-Change-Number: 28657 </div>
<div style="display:none"> Gerrit-PatchSet: 8 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>