[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Correct ITSS port id.

[PraveenX Hodagatta Pranesh (Code Review)]

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28698


Change subject: soc/intel/cannonlake: Correct ITSS port id.
......................................................................

soc/intel/cannonlake: Correct ITSS port id.

According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.

BUG=None
TEST=None

Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/soc/intel/cannonlake/include/soc/pcr_ids.h
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28698/1

diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 891b187..c4a18e8 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -35,7 +35,7 @@
 #define PID_PSF4	0xbd
 #define PID_SCS		0xc0
 #define PID_RTC		0xc3
-#define PID_ITSS	0xc2
+#define PID_ITSS	0xc4
 #define PID_LPC		0xc7
 #define PID_SERIALIO	0xcb
 

-- 
To view, visit https://review.coreboot.org/28698
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Gerrit-Change-Number: 28698
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180920/cf9c2b4e/attachment.html>