[coreboot-gerrit] Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resources

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28672 )

Change subject: soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resources
......................................................................

soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resources

FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.

To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.

TEST=Booted into Linux and checked coreboot log for resource assignment.

Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Nico Huber <nico.h at gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
---
M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
M src/soc/intel/fsp_broadwell_de/vtd.c
2 files changed, 17 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Philipp Deppenwiese: Looks good to me, approved



diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
index 50a4022..edfeafc 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2013 Google, Inc.
  * Copyright (C) 2015-2016 Intel Corp.
- * Copyright (C) 2017 Siemens AG
+ * Copyright (C) 2017-2018 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
 #define VTBAR_OFFSET		0x180
 #define VTBAR_MASK		0xffffe000
 #define VTBAR_ENABLED		0x01
+#define VTBAR_SIZE		0x2000
 
 #define SMM_FEATURE_CONTROL	0x58
 #define  SMM_CPU_SAVE_EN	(1 << 1)
diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c
index ad4a056..e584cfa 100644
--- a/src/soc/intel/fsp_broadwell_de/vtd.c
+++ b/src/soc/intel/fsp_broadwell_de/vtd.c
@@ -17,10 +17,24 @@
 #include <device/pci_ids.h>
 #include <soc/pci_devs.h>
 #include <soc/acpi.h>
+#include <soc/broadwell_de.h>
 
 
+static void vtd_read_resources(struct device *dev)
+{
+	uint32_t vtbar;
+
+	/* Add fixed MMIO resource for VT-d which was set up by the FSP. */
+	vtbar = pci_read_config32(dev, VTBAR_OFFSET);
+	if (vtbar & VTBAR_ENABLED) {
+		mmio_resource(dev, VTBAR_OFFSET,
+				(vtbar & VTBAR_MASK) / KiB, VTBAR_SIZE / KiB);
+	}
+}
+
 static struct device_operations vtd_ops = {
-	.write_acpi_tables        = vtd_write_acpi_tables,
+	.read_resources		= vtd_read_resources,
+	.write_acpi_tables	= vtd_write_acpi_tables,
 };
 
 static const struct pci_driver vtd_driver __pci_driver = {

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Gerrit-Change-Number: 28672
Gerrit-PatchSet: 5
Gerrit-Owner: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: David Hendricks <david.hendricks at gmail.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh at siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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