[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Don't use device_t

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28657


Change subject: sb/intel/bd82x6x/pch.c: Don't use device_t
......................................................................

sb/intel/bd82x6x/pch.c: Don't use device_t

Use of device_t is deprecated.

Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/bd82x6x/pch.c
1 file changed, 5 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28657/1

diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 79cf6bf..bec257b 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -208,9 +208,9 @@
 }
 
 /* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(pci_devfn_t dev)
 {
-	device_t port;
+	pci_devfn_t port;
 	int port_func;
 	int dev_func = PCI_FUNC(dev->path.pci.devfn);
 
@@ -258,7 +258,7 @@
 static void pch_pcie_devicetree_update(
 		struct southbridge_intel_bd82x6x_config *config)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	/*
 	 * hotplug map should also be updated along with their
@@ -312,7 +312,7 @@
 }
 
 /* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(pci_devfn_t dev)
 {
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 	u32 reg32;
@@ -422,7 +422,7 @@
 	}
 }
 
-void pch_enable(device_t dev)
+void pch_enable(pci_devfn_t dev)
 {
 	u32 reg32;
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Gerrit-Change-Number: 28657
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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