<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28657">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x/pch.c: Don't use device_t<br><br>Use of device_t is deprecated.<br><br>Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/bd82x6x/pch.c<br>1 file changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28657/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>index 79cf6bf..bec257b 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/pch.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/pch.c</span><br><span>@@ -208,9 +208,9 @@</span><br><span> }</span><br><span> </span><br><span> /* Check if any port in set X to X+3 is enabled */</span><br><span style="color: hsl(0, 100%, 40%);">-static int pch_pcie_check_set_enabled(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int pch_pcie_check_set_enabled(pci_devfn_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t port;</span><br><span style="color: hsl(120, 100%, 40%);">+        pci_devfn_t port;</span><br><span>    int port_func;</span><br><span>       int dev_func = PCI_FUNC(dev->path.pci.devfn);</span><br><span> </span><br><span>@@ -258,7 +258,7 @@</span><br><span> static void pch_pcie_devicetree_update(</span><br><span>                struct southbridge_intel_bd82x6x_config *config)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span> </span><br><span>         /*</span><br><span>    * hotplug map should also be updated along with their</span><br><span>@@ -312,7 +312,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Special handling for PCIe Root Port devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(pci_devfn_t dev)</span><br><span> {</span><br><span>       struct southbridge_intel_bd82x6x_config *config = dev->chip_info;</span><br><span>         u32 reg32;</span><br><span>@@ -422,7 +422,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(pci_devfn_t dev)</span><br><span> {</span><br><span>       u32 reg32;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28657">change 28657</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28657"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10 </div>
<div style="display:none"> Gerrit-Change-Number: 28657 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>