[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/lenovo/r500: Add mainboard
Arthur Heymans (Code Review)
gerrit at coreboot.org
Mon Sep 17 09:27:14 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28644
Change subject: [WIP]mb/lenovo/r500: Add mainboard
......................................................................
[WIP]mb/lenovo/r500: Add mainboard
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.10.3
- S3 resume (Needs SeaBIOS with sercon disabled)
- Tested in descriptor mode, with vendor FD and ME
Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Models with a sole ATI GPU (needs probing of PEG in romstage)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')
TODO:
- proper dock support
- documentation
note: This board is hard to flash, I had to desolder the flash.
TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.10.3, Debian 9, Linux 4.9
Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/t400/Kconfig
M src/mainboard/lenovo/t400/Kconfig.name
M src/mainboard/lenovo/t400/Makefile.inc
M src/mainboard/lenovo/t400/dsdt.asl
A src/mainboard/lenovo/t400/variants/r500/Makefile.inc
A src/mainboard/lenovo/t400/variants/r500/devicetree.cb
A src/mainboard/lenovo/t400/variants/r500/gpio.c
A src/mainboard/lenovo/t400/variants/t400/Makefile.inc
R src/mainboard/lenovo/t400/variants/t400/devicetree.cb
R src/mainboard/lenovo/t400/variants/t400/gpio.c
10 files changed, 378 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28644/1
diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
index 96f4188..608b668 100644
--- a/src/mainboard/lenovo/t400/Kconfig
+++ b/src/mainboard/lenovo/t400/Kconfig
@@ -1,5 +1,5 @@
if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \
- || BOARD_LENOVO_W500
+ || BOARD_LENOVO_W500 || BOARD_LENOVO_R500
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -11,6 +11,7 @@
select EC_LENOVO_H8
select H8_DOCK_EARLY_INIT
select BOARD_ROMSIZE_KB_8192
+ select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500
select DRIVERS_GENERIC_IOAPIC
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
@@ -29,13 +30,26 @@
string
default lenovo/t400
+config VARIANT_DIR
+ string
+ default "t400" if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 \
+ || BOARD_LENOVO_R400 || BOARD_LENOVO_W500
+ default "r500" if BOARD_LENOVO_R500
+
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T400" if BOARD_LENOVO_T400
default "ThinkPad T500" if BOARD_LENOVO_T500
default "ThinkPad R400" if BOARD_LENOVO_R400
+ default "ThinkPad R500" if BOARD_LENOVO_R500
default "ThinkPad W500" if BOARD_LENOVO_W500
+config DEVICETREE
+ string
+ default "variants/t400/devicetree.cb" if BOARD_LENOVO_T400 \
+ || BOARD_LENOVO_T500 ||BOARD_LENOVO_R400 || BOARD_LENOVO_W500
+ default "variants/r500/devicetree.cb" if BOARD_LENOVO_R500
+
config USBDEBUG_HCD_INDEX
int
default 2
diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name
index d459ce9..a259dde 100644
--- a/src/mainboard/lenovo/t400/Kconfig.name
+++ b/src/mainboard/lenovo/t400/Kconfig.name
@@ -7,5 +7,8 @@
config BOARD_LENOVO_R400
bool "ThinkPad R400"
+config BOARD_LENOVO_R500
+ bool "ThinkPad R500"
+
config BOARD_LENOVO_W500
bool "ThinkPad W500"
diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc
index 7721e03..d0ee153 100644
--- a/src/mainboard/lenovo/t400/Makefile.inc
+++ b/src/mainboard/lenovo/t400/Makefile.inc
@@ -13,9 +13,10 @@
## GNU General Public License for more details.
##
-romstage-y += gpio.c
romstage-y += dock.c
+subdirs-y += variants/$(VARIANT_DIR)/
+
ramstage-y += dock.c
ramstage-y += cstates.c
ramstage-y += blc.c
diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl
index 6ba4774..dd5b574 100644
--- a/src/mainboard/lenovo/t400/dsdt.asl
+++ b/src/mainboard/lenovo/t400/dsdt.asl
@@ -19,6 +19,7 @@
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1
+#define EC_LENOVO_H8_ME_WORKAROUND 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc
new file mode 100644
index 0000000..6048409
--- /dev/null
+++ b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += gpio.c
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t400/variants/r500/devicetree.cb b/src/mainboard/lenovo/t400/variants/r500/devicetree.cb
new file mode 100644
index 0000000..8ea5f43
--- /dev/null
+++ b/src/mainboard/lenovo/t400/variants/r500/devicetree.cb
@@ -0,0 +1,224 @@
+chip northbridge/intel/gm45
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ register "gfx.use_spread_spectrum_clock" = "1"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_mPGA478MN
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Enable Super LFM
+ register "slfm" = "1"
+
+ # Enable C5, C6
+ register "c5" = "1"
+ register "c6" = "1"
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x20e0
+ end # host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on # VGA
+ subsystemid 0x17aa 0x20e4
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.1 on
+ subsystemid 0x17aa 0x20e4
+ end # Display
+ device pci 03.0 off end # ME
+ device pci 03.1 off end # ME
+ device pci 03.2 off end # ME
+ device pci 03.3 off end # ME
+ chip southbridge/intel/i82801ix
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ register "gpi8_routing" = "2"
+ register "gpe0_en" = "0x01000000"
+ register "gpi1_routing" = "2"
+
+ # Set AHCI mode, enable ports 1 and 2.
+ register "sata_port_map" = "0x03"
+ register "sata_clock_request" = "1"
+ register "sata_traffic_monitor" = "0"
+
+ # Set c-state support
+ register "c4onc3_enable" = "1"
+ register "c5_enable" = "1"
+ register "c6_enable" = "1"
+
+ # Set thermal throttling to 75%.
+ register "throttle_duty" = "THTL_75_0"
+
+ # Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe).
+ register "pcie_slot_implemented" = "0x3b"
+ # Set power limits to 10 * 10^0 watts.
+ # Maybe we should set less for Mini PCIe.
+ register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }"
+
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "1"
+ register "base" = "(void *)0xfec00000"
+ device ioapic 2 on end
+ end
+
+ device pci 19.0 off end # LAN
+ device pci 1a.0 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1a.1 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1a.2 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1a.7 on # EHCI
+ subsystemid 0x17aa 0x20f1
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1b.0 on # HD Audio
+ subsystemid 0x17aa 0x20f2
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x17aa 0x20f3 # WWAN
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x17aa 0x20f3 # WLAN
+ end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on # PCIe Port #4
+ subsystemid 0x17aa 0x20f3 # Expresscard
+ end # PCIe Port #4
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x17aa 0x20f3
+ end
+ device pci 1c.5 on # PCIe Port #6
+ subsystemid 0x17aa 0x20f3 # Ethernet NIC
+ end
+ device pci 1d.0 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1d.1 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1d.2 on # UHCI
+ subsystemid 0x17aa 0x20f0
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1d.7 on # EHCI
+ subsystemid 0x17aa 0x20f1
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1e.0 on # PCI
+ subsystemid 0x17aa 0x20f4
+ end
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x17aa 0x20f5
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x05"
+ register "config2" = "0xa0"
+ register "config3" = "0x40"
+
+ register "beepmask0" = "0xfe"
+ register "beepmask1" = "0x96"
+ register "has_power_management_beeps" = "1"
+
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xf4"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x87"
+ register "event7_enable" = "0x09"
+ register "event8_enable" = "0x5b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x83"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+
+ register "has_bdc_detection" = "1"
+ register "bdc_gpio_num" = "48"
+ register "bdc_gpio_lvl" = "0"
+ end
+
+ chip superio/nsc/pc87382
+ device pnp 164e.2 off end # IR
+ device pnp 164e.3 off end # Serial Port
+ device pnp 164e.7 on # GPIO
+ io 0x60 = 0x1680
+ end
+ device pnp 164e.19 on # DLPC
+ io 0x60 = 0x164c
+ end
+ end
+
+ chip superio/nsc/pc87384
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x3bc
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off end # Serial Port / IR
+ device pnp 2e.3 on # Serial Port
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x1620
+ end
+ end
+ end
+ device pci 1f.2 on # SATA/IDE 1
+ subsystemid 0x17aa 0x20f8
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x17aa 0x20f9
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1f.5 off end # SATA/IDE 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/t400/variants/r500/gpio.c b/src/mainboard/lenovo/t400/variants/r500/gpio.c
new file mode 100644
index 0000000..a1cc458
--- /dev/null
+++ b/src/mainboard/lenovo/t400/variants/r500/gpio.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_OUTPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio41 = GPIO_LEVEL_HIGH,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc
new file mode 100644
index 0000000..6048409
--- /dev/null
+++ b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += gpio.c
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/variants/t400/devicetree.cb
similarity index 100%
rename from src/mainboard/lenovo/t400/devicetree.cb
rename to src/mainboard/lenovo/t400/variants/t400/devicetree.cb
diff --git a/src/mainboard/lenovo/t400/gpio.c b/src/mainboard/lenovo/t400/variants/t400/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/t400/gpio.c
rename to src/mainboard/lenovo/t400/variants/t400/gpio.c
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Gerrit-Change-Number: 28644
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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