<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28644">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/lenovo/r500: Add mainboard<br><br>Tested:<br>- Ethernet NIC<br>- Wifi RFKill<br>- USB<br>- LVDS, VGA with libgfxinit<br>- Booting with dock attached (COM1)<br>- Keyboard, trackpoint<br>- SeaBIOS 1.10.3<br>- S3 resume (Needs SeaBIOS with sercon disabled)<br>- Tested in descriptor mode, with vendor FD and ME<br><br>Untested:<br>- SATA (likely works)<br>- Trackpad (my cable is broken, likely works)<br>- Displayport (likely works)<br>- Descriptorless mode<br>- DVD drive<br>- Extra battery<br><br>Does not work:<br>- Dock hotplug<br>- Quad core CPU (hangs during AP init, probably needs hardware mod)<br>- Models with a sole ATI GPU (needs probing of PEG in romstage)<br>- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee<br>/sys/bus/pci/rescan')<br><br>TODO:<br>- proper dock support<br>- documentation<br><br>note: This board is hard to flash, I had to desolder the flash.<br><br>TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.10.3, Debian 9, Linux 4.9<br><br>Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/t400/Kconfig<br>M src/mainboard/lenovo/t400/Kconfig.name<br>M src/mainboard/lenovo/t400/Makefile.inc<br>M src/mainboard/lenovo/t400/dsdt.asl<br>A src/mainboard/lenovo/t400/variants/r500/Makefile.inc<br>A src/mainboard/lenovo/t400/variants/r500/devicetree.cb<br>A src/mainboard/lenovo/t400/variants/r500/gpio.c<br>A src/mainboard/lenovo/t400/variants/t400/Makefile.inc<br>R src/mainboard/lenovo/t400/variants/t400/devicetree.cb<br>R src/mainboard/lenovo/t400/variants/t400/gpio.c<br>10 files changed, 378 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28644/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig</span><br><span>index 96f4188..608b668 100644</span><br><span>--- a/src/mainboard/lenovo/t400/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/t400/Kconfig</span><br><span>@@ -1,5 +1,5 @@</span><br><span> if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 || BOARD_LENOVO_R400 \</span><br><span style="color: hsl(0, 100%, 40%);">- || BOARD_LENOVO_W500</span><br><span style="color: hsl(120, 100%, 40%);">+ || BOARD_LENOVO_W500 || BOARD_LENOVO_R500</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span> def_bool y</span><br><span>@@ -11,6 +11,7 @@</span><br><span> select EC_LENOVO_H8</span><br><span> select H8_DOCK_EARLY_INIT</span><br><span> select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500</span><br><span> select DRIVERS_GENERIC_IOAPIC</span><br><span> select HAVE_MP_TABLE</span><br><span> select HAVE_ACPI_TABLES</span><br><span>@@ -29,13 +30,26 @@</span><br><span> string</span><br><span> default lenovo/t400</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "t400" if BOARD_LENOVO_T400 || BOARD_LENOVO_T500 \</span><br><span style="color: hsl(120, 100%, 40%);">+ || BOARD_LENOVO_R400 || BOARD_LENOVO_W500</span><br><span style="color: hsl(120, 100%, 40%);">+ default "r500" if BOARD_LENOVO_R500</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "ThinkPad T400" if BOARD_LENOVO_T400</span><br><span> default "ThinkPad T500" if BOARD_LENOVO_T500</span><br><span> default "ThinkPad R400" if BOARD_LENOVO_R400</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad R500" if BOARD_LENOVO_R500</span><br><span> default "ThinkPad W500" if BOARD_LENOVO_W500</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/t400/devicetree.cb" if BOARD_LENOVO_T400 \</span><br><span style="color: hsl(120, 100%, 40%);">+ || BOARD_LENOVO_T500 ||BOARD_LENOVO_R400 || BOARD_LENOVO_W500</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/r500/devicetree.cb" if BOARD_LENOVO_R500</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config USBDEBUG_HCD_INDEX</span><br><span> int</span><br><span> default 2</span><br><span>diff --git a/src/mainboard/lenovo/t400/Kconfig.name b/src/mainboard/lenovo/t400/Kconfig.name</span><br><span>index d459ce9..a259dde 100644</span><br><span>--- a/src/mainboard/lenovo/t400/Kconfig.name</span><br><span>+++ b/src/mainboard/lenovo/t400/Kconfig.name</span><br><span>@@ -7,5 +7,8 @@</span><br><span> config BOARD_LENOVO_R400</span><br><span> bool "ThinkPad R400"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_R500</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad R500"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOARD_LENOVO_W500</span><br><span> bool "ThinkPad W500"</span><br><span>diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc</span><br><span>index 7721e03..d0ee153 100644</span><br><span>--- a/src/mainboard/lenovo/t400/Makefile.inc</span><br><span>+++ b/src/mainboard/lenovo/t400/Makefile.inc</span><br><span>@@ -13,9 +13,10 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gpio.c</span><br><span> romstage-y += dock.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += variants/$(VARIANT_DIR)/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ramstage-y += dock.c</span><br><span> ramstage-y += cstates.c</span><br><span> ramstage-y += blc.c</span><br><span>diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl</span><br><span>index 6ba4774..dd5b574 100644</span><br><span>--- a/src/mainboard/lenovo/t400/dsdt.asl</span><br><span>+++ b/src/mainboard/lenovo/t400/dsdt.asl</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span> #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span> #define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_LENOVO_H8_ME_WORKAROUND 1</span><br><span> </span><br><span> DefinitionBlock(</span><br><span> "dsdt.aml",</span><br><span>diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..6048409</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/lenovo/t400/variants/r500/devicetree.cb b/src/mainboard/lenovo/t400/variants/r500/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..8ea5f43</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t400/variants/r500/devicetree.cb</span><br><span>@@ -0,0 +1,224 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/gm45</span><br><span style="color: hsl(120, 100%, 40%);">+ # IGD Displays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_mPGA478MN</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x</span><br><span style="color: hsl(120, 100%, 40%);">+ # Magic APIC ID to locate this chip</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Super LFM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "slfm" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable C5, C6</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c5" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c6" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "2048"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20e0</span><br><span style="color: hsl(120, 100%, 40%);">+ end # host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on end # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on # VGA</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20e4</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20e4</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Display</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.2 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.3 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi8_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x01000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set AHCI mode, enable ports 1 and 2.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x03"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_clock_request" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_traffic_monitor" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set c-state support</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c4onc3_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c5_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c6_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set thermal throttling to 75%.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "throttle_duty" = "THTL_75_0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable PCIe ports 1,2,4,5,6 as slots (Mini * PCIe).</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_slot_implemented" = "0x3b"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set power limits to 10 * 10^0 watts.</span><br><span style="color: hsl(120, 100%, 40%);">+ # Maybe we should set less for Mini PCIe.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_power_limits" = "{ { 41, 0 }, { 41, 0 }, { 0, 0 }, { 41, 0 }, { 41, 0 }, { 41, 0 } }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 1, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/ioapic</span><br><span style="color: hsl(120, 100%, 40%);">+ register "have_isa_interrupts" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq_on_fsb" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "enable_virtual_wire" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "base" = "(void *)0xfec00000"</span><br><span style="color: hsl(120, 100%, 40%);">+ device ioapic 2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.1 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTB 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.2 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTC 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.7 on # EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f1</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTC 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # HD Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f2</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f3 # WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f3 # WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f3 # Expresscard</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 on # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f3 # Ethernet NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTB 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on # UHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f0</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTC 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on # EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f1</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTA 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on # PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f5</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/pmh7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ register "backlight_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dock_event_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/h8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.2 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x66 = 0x1604</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config0" = "0xa6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config1" = "0x05"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config2" = "0xa0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config3" = "0x40"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask0" = "0xfe"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask1" = "0x96"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_management_beeps" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event2_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event3_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event4_enable" = "0xf4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event5_enable" = "0x3c"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event6_enable" = "0x87"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event7_enable" = "0x09"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event8_enable" = "0x5b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event9_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventa_enable" = "0x83"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventb_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventc_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventd_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_bdc_detection" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bdc_gpio_num" = "48"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "bdc_gpio_lvl" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nsc/pc87382</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 164e.2 off end # IR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 164e.3 off end # Serial Port</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 164e.7 on # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x1680</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 164e.19 on # DLPC</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x164c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nsc/pc87384</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel Port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3bc</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off end # Serial Port / IR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # Serial Port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 on # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x1620</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA/IDE 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f8</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTB 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x20f9</span><br><span style="color: hsl(120, 100%, 40%);">+ ioapic_irq 2 INTC 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA/IDE 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/lenovo/t400/variants/r500/gpio.c b/src/mainboard/lenovo/t400/variants/r500/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a1cc458</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t400/variants/r500/gpio.c</span><br><span>@@ -0,0 +1,131 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..6048409</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/variants/t400/devicetree.cb</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/t400/devicetree.cb</span><br><span>rename to src/mainboard/lenovo/t400/variants/t400/devicetree.cb</span><br><span>diff --git a/src/mainboard/lenovo/t400/gpio.c b/src/mainboard/lenovo/t400/variants/t400/gpio.c</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/t400/gpio.c</span><br><span>rename to src/mainboard/lenovo/t400/variants/t400/gpio.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28644">change 28644</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28644"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815 </div>
<div style="display:none"> Gerrit-Change-Number: 28644 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>