[coreboot-gerrit] Change in coreboot[rampayload]: WIP: Port libpayload to riscv
Philipp Hug (Code Review)
gerrit at coreboot.org
Fri Sep 14 16:40:12 CEST 2018
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28606
Change subject: WIP: Port libpayload to riscv
......................................................................
WIP: Port libpayload to riscv
Work-in-progress port of libpayload to RISC-V
Do not merge yet
Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded
---
M payloads/external/LinuxBoot/Kconfig
M payloads/external/LinuxBoot/Kconfig.name
M payloads/external/LinuxBoot/Makefile
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/arch/riscv/Kconfig
A payloads/libpayload/arch/riscv/Makefile.inc
A payloads/libpayload/arch/riscv/coreboot.c
A payloads/libpayload/arch/riscv/head.S
A payloads/libpayload/arch/riscv/libpayload.ldscript
A payloads/libpayload/arch/riscv/main.c
M payloads/libpayload/bin/lpgcc
A payloads/libpayload/configs/defconfig-riscv
A payloads/libpayload/include/riscv/arch/asm.h
A payloads/libpayload/include/riscv/arch/barrier.h
A payloads/libpayload/include/riscv/arch/cache.h
A payloads/libpayload/include/riscv/arch/io.h
A payloads/libpayload/include/riscv/arch/types.h
A payloads/libpayload/include/riscv/arch/virtual.h
M payloads/linuxcheck/Makefile
21 files changed, 779 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28606/1
diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
index 8acb542..c359a57 100644
--- a/payloads/external/LinuxBoot/Kconfig
+++ b/payloads/external/LinuxBoot/Kconfig
@@ -37,6 +37,12 @@
help
AARCH64 kernel and initramfs
+config LINUXBOOT_RISCV
+ bool "riscv"
+ depends on ARCH_RISCV
+ help
+ RISCV64 kernel and initramfs
+
endchoice
config LINUXBOOT_ARCH
@@ -44,6 +50,7 @@
default "amd64" if LINUXBOOT_X86_64
default "386" if LINUXBOOT_X86
default "arm64" if LINUXBOOT_ARM64
+ default "riscv" if LINUXBOOT_RISCV
choice
prompt "Kernel version"
diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name
index 18438c7..c59a8bc 100644
--- a/payloads/external/LinuxBoot/Kconfig.name
+++ b/payloads/external/LinuxBoot/Kconfig.name
@@ -14,7 +14,7 @@
config PAYLOAD_LINUXBOOT
bool "LinuxBoot"
- depends on ARCH_X86 || ARCH_ARM64
+ depends on ARCH_X86 || ARCH_ARM64 || ARCH_RISCV
help
Select this option if you want to build a coreboot image
with a LinuxBoot payload. If you don't know what this is
diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
index c051389..71b3ab2 100644
--- a/payloads/external/LinuxBoot/Makefile
+++ b/payloads/external/LinuxBoot/Makefile
@@ -29,6 +29,9 @@
else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux-
ARCH?=arm64
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv)
+LINUXBOOT_COMPILE?=$(XGCCPATH)/riscv64-elf-
+ARCH?=riscv
endif
OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy
@@ -36,10 +39,11 @@
all: payload
toolchain:
- if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
- echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \
- exit 1; \
- fi
+ echo $(LINUXBOOT_COMPILE)
+ #if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
+ #echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \
+ #exit 1; \
+ #fi
$(kernel_dir)/.config:
echo " WWW Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
@@ -59,15 +63,21 @@
cp x86_64/defconfig $(kernel_dir)/.config
else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
cp arm64/defconfig $(kernel_dir)/.config
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv)
+ cp riscv/defconfig $(kernel_dir)/.config
endif
ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64))
$(kernel_dir)/arch/x86/boot/bzImage: config toolchain
else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
$(kernel_dir)/vmlinux: config toolchain
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv)
+$(kernel_dir)/vmlinux: config toolchain
endif
echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+ echo "BEFOR DEF"
$(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
+ echo "AFTER DEF"
$(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64))
@@ -86,6 +96,9 @@
$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),riscv)
+$(project_dir)/kernel-image: $(kernel_dir)/vmlinux
+ $(OBJCOPY) -O binary $< $@
endif
ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 3cd8ba6..178945b 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -119,6 +119,11 @@
help
Support the MIPS architecture
+config ARCH_RISCV
+ bool "RISCV"
+ help
+ Support the RISCV architecture
+
endchoice
config MULTIBOOT
@@ -148,12 +153,13 @@
default 0x04000000 if ARCH_ARM
default 0x80100000 if ARCH_ARM64
default 0x00000000 if ARCH_MIPS
+ default 0x81000000 if ARCH_RISCV
default 0x00100000 if ARCH_X86
help
This is the base address for the payload.
If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS,
- 0x04000000 on ARM or 0x80100000 on ARM64.
+ 0x04000000 on ARM or 0x80100000 on ARM64 or 0x81000000 on RISCV.
endmenu
@@ -450,4 +456,5 @@
source "arch/arm/Kconfig"
source "arch/arm64/Kconfig"
source "arch/mips/Kconfig"
+source "arch/riscv/Kconfig"
source "arch/x86/Kconfig"
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index 1a0acf1..e01115e 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -96,6 +96,7 @@
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
ARCH-y := $(ARCHDIR-y)
@@ -105,6 +106,7 @@
ARCH-$(CONFIG_LP_ARCH_ARM) := arm
ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCH-$(CONFIG_LP_ARCH_X86) := x86_32
+ARCH-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCH-$(CONFIG_LP_ARCH_MIPS) := mips
# Three cases where we don't need fully populated $(obj) lists:
diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc
index 7787762..f204722 100644
--- a/payloads/libpayload/Makefile.inc
+++ b/payloads/libpayload/Makefile.inc
@@ -34,6 +34,7 @@
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
DESTDIR ?= install
@@ -83,6 +84,9 @@
$(obj)/libpayload.a: $(foreach class,$(libraries),$$($(class)-objs))
printf " AR $(subst $(CURDIR)/,,$(@))\n"
+ echo $(ARCH-y)
+ echo $(AR)
+ echo $(AR_riscv)
$(AR) rc $@ $^
$(obj)/%.a: $$(%-objs)
diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig
new file mode 100644
index 0000000..b747256
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the libpayload project.
+##
+## Copyright (c) 2012 Google Inc.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+## derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+if ARCH_RISCV
+
+config ARCH_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select LITTLE_ENDIAN
+
+endif
diff --git a/payloads/libpayload/arch/riscv/Makefile.inc b/payloads/libpayload/arch/riscv/Makefile.inc
new file mode 100644
index 0000000..4c5c78b
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Makefile.inc
@@ -0,0 +1,32 @@
+##
+## This file is part of the libpayload project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+## derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+head.o-y += head.S
+
+libc-y += main.c coreboot.c
diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c
new file mode 100644
index 0000000..a25c51a
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/coreboot.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <coreboot_tables.h>
+
+/* This pointer gets set in head.S and is passed in from coreboot. */
+void *cb_header_ptr;
+
+/* == Architecture specific == */
+
+int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
+{
+ switch(rec->tag) {
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+int get_coreboot_info(struct sysinfo_t *info)
+{
+ return cb_parse_header(cb_header_ptr, 1, info);
+}
+
+void *get_cb_header_ptr(void)
+{
+ return cb_header_ptr;
+}
diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S
new file mode 100644
index 0000000..c7f793f
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/head.S
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/*
+ * Our entry point
+ */
+ENTRY(_entry)
+
+ /* Save off the location of the coreboot tables */
+ // TODO
+
+ /* Setup exception stack */
+ // TODO
+
+ /* Setup new stack */
+ // TODO
+ csrr a0, mhartid
+ la t0, _stack
+ li t1, 0xDEADBEEF
+ sd t1, 0(t0)
+ add sp, t0, 0
+
+ /* Let's rock. */
+ tail start_main
+
+ENDPROC(_entry)
+
+.align 4
+1:
+.quad cb_header_ptr
+2:
+.quad _stack
diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript
new file mode 100644
index 0000000..149c121
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/libpayload.ldscript
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv","elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+
+ENTRY(_entry)
+
+SECTIONS
+{
+ . = CONFIG_LP_BASE_ADDRESS;
+
+ //. = ALIGN(16);
+ _start = .;
+
+ .text : {
+ *(.text._entry)
+ *(.text)
+ *(.text.*)
+ }
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+
+ .data : {
+ *(.data)
+ *(.data.*)
+ }
+
+ _edata = .;
+
+ .bss : {
+ *(.sbss)
+ *(.sbss.*)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ /* Stack and heap */
+
+ . = ALIGN(16);
+ _heap = .;
+ . += CONFIG_LP_HEAP_SIZE;
+ . = ALIGN(16);
+ _eheap = .;
+
+ _estack = .;
+ . += CONFIG_LP_STACK_SIZE;
+ . = ALIGN(16);
+ _stack = .;
+ }
+
+ _end = .;
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.note*)
+ }
+}
diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c
new file mode 100644
index 0000000..4c288ac
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/main.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+
+unsigned int main_argc; /**< The argc value to pass to main() */
+
+/** The argv value to pass to main() */
+char *main_argv[MAX_ARGC_COUNT];
+
+/**
+ * This is our C entry function - set up the system
+ * and jump into the payload entry point.
+ */
+void start_main(void);
+void start_main(void)
+{
+ extern int main(int argc, char **argv);
+
+ /* Gather system information. */
+ lib_get_sysinfo();
+
+#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+ console_init();
+#endif
+
+ //exception_init(); TODO
+
+ /*
+ * Any other system init that has to happen before the
+ * user gets control goes here.
+ */
+
+ /*
+ * Go to the entry point.
+ * In the future we may care about the return value.
+ */
+
+ (void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
+
+ /*
+ * Returning here will go to the _leave function to return
+ * us to the original context.
+ */
+}
diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
index b3ef342..2faf113 100755
--- a/payloads/libpayload/bin/lpgcc
+++ b/payloads/libpayload/bin/lpgcc
@@ -86,6 +86,12 @@
_ARCHEXTRA=""
_ARCH=mips
fi
+if [ "$CONFIG_LP_ARCH_RISCV" = "y" ]; then
+ _ARCHINCDIR=$_INCDIR/riscv
+ _ARCHLIBDIR=$_LIBDIR/riscv
+ _ARCHEXTRA=""
+ _ARCH=riscv
+fi
if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
_ARCHINCDIR=$_INCDIR/x86
_ARCHLIBDIR=$_LIBDIR/x86
diff --git a/payloads/libpayload/configs/defconfig-riscv b/payloads/libpayload/configs/defconfig-riscv
new file mode 100644
index 0000000..2ce2bc5
--- /dev/null
+++ b/payloads/libpayload/configs/defconfig-riscv
@@ -0,0 +1,3 @@
+CONFIG_LP_ARCH_RISCV=y
+CONFIG_LP_TINYCURSES=n
+CONFIG_LP_USB=n
diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h
new file mode 100644
index 0000000..de44482
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/asm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ */
+
+#ifndef __ARM64_ASM_H
+#define __ARM64_ASM_H
+
+# define ARM64(x...) x
+# define W(instr) instr
+
+#define ALIGN .align 2
+
+#define ENDPROC(name) \
+ .type name, %function; \
+ END(name)
+
+#define ENTRY(name) \
+ .section .text.name, "ax", %progbits; \
+ .global name; \
+ ALIGN; \
+ name:
+
+#define END(name) \
+ .size name, .-name
+
+#endif /* __ARM64_ASM_H */
diff --git a/payloads/libpayload/include/riscv/arch/barrier.h b/payloads/libpayload/include/riscv/arch/barrier.h
new file mode 100644
index 0000000..0b55df6
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/barrier.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (C) 2003-2004 Olivier Houchard
+ * Copyright (C) 1994-1997 Mark Brinicombe
+ * Copyright (C) 1994 Brini
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ARCH_BARRIER_H_
+#define __ARCH_BARRIER_H__
+
+#include <arch/cache.h>
+
+/*
+ * Description of different memory barriers introduced:
+ *
+ * Memory barrier(mb) - Guarantees that all memory accesses specified before the
+ * barrier will happen before all memory accesses specified after the barrier
+ *
+ * Read memory barrier (rmb) - Guarantees that all read memory accesses
+ * specified before the barrier will happen before all read memory accesses
+ * specified after the barrier
+ *
+ * Write memory barrier (wmb) - Guarantees that all write memory accesses
+ * specified before the barrier will happen before all write memory accesses
+ * specified after the barrier
+ */
+
+#define mb()
+#define rmb()
+#define wmb()
+
+#endif /* __ARCH_BARRIER_H__ */
diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h
new file mode 100644
index 0000000..820bee9
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/cache.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.h: Cache maintenance API for RISCV
+ */
+
+#ifndef RISCV_CACHE_H
+#define RISCV_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * Cache maintenance API
+ */
+
+/* dcache clean and invalidate all (on current level given by CCSELR) */
+void dcache_clean_invalidate_all(void);
+
+/* dcache clean by virtual address to PoC */
+void dcache_clean_by_mva(void const *addr, size_t len);
+
+/* dcache clean and invalidate by virtual address to PoC */
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
+
+/* dcache invalidate by virtual address to PoC */
+void dcache_invalidate_by_mva(void const *addr, size_t len);
+
+void dcache_clean_all(void);
+
+/* dcache invalidate all (on current level given by CCSELR) */
+void dcache_invalidate_all(void);
+
+/* returns number of bytes per cache line */
+unsigned int dcache_line_bytes(void);
+
+/* dcache and MMU disable */
+void dcache_mmu_disable(void);
+
+/* dcache and MMU enable */
+void dcache_mmu_enable(void);
+
+/* perform all icache/dcache maintenance needed after loading new code */
+void cache_sync_instructions(void);
+
+/* Ensure that loaded program segment is synced back from cache to PoC */
+void arch_program_segment_loaded(void const *addr, size_t len);
+
+/* tlb invalidate all */
+void tlb_invalidate_all(void);
+
+/* Invalidate all of the instruction cache for PE to PoU. */
+static inline void icache_invalidate_all(void)
+{
+ return;
+}
+
+#endif /* RISCV_CACHE_H */
diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h
new file mode 100644
index 0000000..8413b61
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/io.h
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_IO_H
+#define _ARCH_IO_H
+
+#include <stdint.h>
+#include <arch/cache.h>
+//#include <arch/lib_helpers.h>
+
+/*
+ * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32
+ * instead for future development.
+ *
+ * TODO: make the existing code use read8/16/32 and write8/16/32 then remove
+ * readb/w/l and writeb/w/l.
+ */
+
+static inline uint8_t readb(volatile const void *_a)
+{
+ return *(volatile const uint8_t *)_a;
+}
+
+static inline uint16_t readw(volatile const void *_a)
+{
+ return *(volatile const uint16_t *)_a;
+}
+
+static inline uint32_t readl(volatile const void *_a)
+{
+ return *(volatile const uint32_t *)_a;
+}
+
+static inline void writeb(uint8_t _v, volatile void *_a)
+{
+ *(volatile uint8_t *)_a = _v;
+}
+
+static inline void writew(uint16_t _v, volatile void *_a)
+{
+ *(volatile uint16_t *)_a = _v;
+}
+
+static inline void writel(uint32_t _v, volatile void *_a)
+{
+ *(volatile uint32_t *)_a = _v;
+}
+
+static inline uint8_t read8(const void *addr)
+{
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const void *addr)
+{
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const void *addr)
+{
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(void *addr, uint8_t val)
+{
+ *(volatile uint8_t *)addr = val;
+}
+
+static inline void write16(void *addr, uint16_t val)
+{
+ *(volatile uint16_t *)addr = val;
+}
+
+static inline void write32(void *addr, uint32_t val)
+{
+ *(volatile uint32_t *)addr = val;
+}
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h
new file mode 100644
index 0000000..1bd815b
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/types.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_TYPES_H
+#define _ARCH_TYPES_H
+
+typedef unsigned char uint8_t;
+typedef unsigned char u8;
+typedef signed char int8_t;
+typedef signed char s8;
+
+typedef unsigned short uint16_t;
+typedef unsigned short u16;
+typedef signed short int16_t;
+typedef signed short s16;
+
+typedef unsigned int uint32_t;
+typedef unsigned int u32;
+typedef signed int int32_t;
+typedef signed int s32;
+
+typedef unsigned long long uint64_t;
+typedef unsigned long long u64;
+typedef signed long long int64_t;
+typedef signed long long s64;
+
+typedef long time_t;
+typedef long suseconds_t;
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h
new file mode 100644
index 0000000..328c3aa
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/virtual.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_VIRTUAL_H
+#define _ARCH_VIRTUAL_H
+
+extern unsigned long virtual_offset;
+
+#define virt_to_phys(virt) ((unsigned long) (virt) + virtual_offset)
+#define phys_to_virt(phys) ((void *) ((unsigned long) (phys) - virtual_offset))
+
+#define virt_to_bus(addr) virt_to_phys(addr)
+#define bus_to_virt(addr) phys_to_virt(addr)
+
+#endif
diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile
index b967369..3299397 100644
--- a/payloads/linuxcheck/Makefile
+++ b/payloads/linuxcheck/Makefile
@@ -6,18 +6,23 @@
CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib
ifeq ($(CONFIG_ARCH_X86),y)
TARGETARCH = i386
+DEFCONFIG = defconfig
+endif
+ifeq ($(CONFIG_ARCH_RISCV),y)
+TARGETARCH = riscv
+DEFCONFIG = defconfig-riscv
endif
all: linuxcheck.elf
$(LIBPAYLOAD_DIR):
- $(MAKE) -C ../libpayload $(LPOPTS) defconfig
+ $(MAKE) -C ../libpayload $(LPOPTS) $(DEFCONFIG)
$(MAKE) -C ../libpayload $(LPOPTS)
$(MAKE) -C ../libpayload $(LPOPTS) install
ifneq ($(strip $(wildcard libpayload)),)
include $(XCOMPILE)
-LPGCC = CC="$(GCC_CC_x86_32)" "$(LIBPAYLOAD_DIR)/bin/lpgcc"
+LPGCC = CC="$(GCC_CC_riscv)" "$(LIBPAYLOAD_DIR)/bin/lpgcc"
%.elf: %.c Makefile
$(LPGCC) $(CFLAGS) -o $*.elf $*.c $(TARGETARCH).c
else
--
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Gerrit-Project: coreboot
Gerrit-Branch: rampayload
Gerrit-MessageType: newchange
Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded
Gerrit-Change-Number: 28606
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
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