[coreboot-gerrit] Change in coreboot[master]: soc/sifive/fu540: Get SDRAM controller out of reset

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28583


Change subject: soc/sifive/fu540: Get SDRAM controller out of reset
......................................................................

soc/sifive/fu540: Get SDRAM controller out of reset

Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874
---
M src/soc/sifive/fu540/clock.c
1 file changed, 34 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28583/1

diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index a59a1e8..2f55bf1 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -68,6 +68,12 @@
 
 #define PRCI_CORECLKSEL_CORECLKSEL 1
 
+#define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1)  << 0)
+#define PRCI_DEVICESRESET_DDR_AXI_RST_N(x)  (((x) & 0x1)  << 1)
+#define PRCI_DEVICESRESET_DDR_AHB_RST_N(x)  (((x) & 0x1)  << 2)
+#define PRCI_DEVICESRESET_DDR_PHY_RST_N(x)  (((x) & 0x1)  << 3)
+#define PRCI_DEVICESRESET_GEMGXL_RST_N(x)   (((x) & 0x1)  << 5)
+
 /*
  * Set coreclk according to the SiFive FU540-C000 Manual
  * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
@@ -176,5 +182,33 @@
 
 	// put DDR and ethernet in reset
 	write32(&prci->devicesresetreg, 0);
+
 	init_pll_ddr();
+
+	// The following code and its comments is mostly derived from the SiFive
+	// u540 bootloader.
+	// https://github.com/sifive/freedom-u540-c000-bootloader
+
+	// get DDR out of reset
+	write32(&prci->devicesresetreg, PRCI_DEVICESRESET_DDR_CTRL_RST_N(1));
+
+	// HACK to get the '1 full controller clock cycle'.
+	asm volatile ("fence");
+
+	// get DDR out of reset
+	write32(&prci->devicesresetreg,
+		PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) |
+		PRCI_DEVICESRESET_DDR_AXI_RST_N(1) |
+		PRCI_DEVICESRESET_DDR_AHB_RST_N(1) |
+		PRCI_DEVICESRESET_DDR_PHY_RST_N(1));
+
+	// HACK to get the '1 full controller clock cycle'.
+	asm volatile ("fence");
+
+	// These take like 16 cycles to actually propagate. We can't go sending
+	// stuff before they come out of reset. So wait.
+	// TODO: Add a register to read the current reset states, or DDR Control
+	// device?
+	for (int i = 0; i < 256; i++)
+		asm volatile ("nop");
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874
Gerrit-Change-Number: 28583
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
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