<p>Philipp Hug has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28583">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/sifive/fu540: Get SDRAM controller out of reset<br><br>Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874<br>---<br>M src/soc/sifive/fu540/clock.c<br>1 file changed, 34 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28583/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c</span><br><span>index a59a1e8..2f55bf1 100644</span><br><span>--- a/src/soc/sifive/fu540/clock.c</span><br><span>+++ b/src/soc/sifive/fu540/clock.c</span><br><span>@@ -68,6 +68,12 @@</span><br><span> </span><br><span> #define PRCI_CORECLKSEL_CORECLKSEL 1</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DEVICESRESET_DDR_CTRL_RST_N(x) (((x) & 0x1) << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Set coreclk according to the SiFive FU540-C000 Manual</span><br><span> * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/</span><br><span>@@ -176,5 +182,33 @@</span><br><span> </span><br><span> // put DDR and ethernet in reset</span><br><span> write32(&prci->devicesresetreg, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> init_pll_ddr();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // The following code and its comments is mostly derived from the SiFive</span><br><span style="color: hsl(120, 100%, 40%);">+ // u540 bootloader.</span><br><span style="color: hsl(120, 100%, 40%);">+ // https://github.com/sifive/freedom-u540-c000-bootloader</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // get DDR out of reset</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->devicesresetreg, PRCI_DEVICESRESET_DDR_CTRL_RST_N(1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // HACK to get the '1 full controller clock cycle'.</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("fence");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // get DDR out of reset</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&prci->devicesresetreg,</span><br><span style="color: hsl(120, 100%, 40%);">+ PRCI_DEVICESRESET_DDR_CTRL_RST_N(1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ PRCI_DEVICESRESET_DDR_AXI_RST_N(1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ PRCI_DEVICESRESET_DDR_AHB_RST_N(1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ PRCI_DEVICESRESET_DDR_PHY_RST_N(1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // HACK to get the '1 full controller clock cycle'.</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("fence");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // These take like 16 cycles to actually propagate. We can't go sending</span><br><span style="color: hsl(120, 100%, 40%);">+ // stuff before they come out of reset. So wait.</span><br><span style="color: hsl(120, 100%, 40%);">+ // TODO: Add a register to read the current reset states, or DDR Control</span><br><span style="color: hsl(120, 100%, 40%);">+ // device?</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < 256; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ asm volatile ("nop");</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28583">change 28583</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28583"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874 </div>
<div style="display:none"> Gerrit-Change-Number: 28583 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Hug <philipp@hug.cx> </div>