[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add FSP CAR Init support for CFL

PraveenX Hodagatta Pranesh (Code Review) gerrit at coreboot.org
Wed Sep 12 10:52:45 CEST 2018 

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28581


Change subject: soc/intel/cannonlake: Add FSP CAR Init support for CFL
......................................................................

soc/intel/cannonlake: Add FSP CAR Init support for CFL

FSP2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram.  Add TempRamInit & TempRamExit usage to
Coffeelake SoC when CONFIG_FSP_CAR is selected.

coffeelake CRB's RVP11 & RVP8 uses entire FSP including FSP-T to setup
CAR, MP init & MTRR programming without using coreboot Enhanced-NEM mode
and coreboot MP init.

BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.

Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S
A src/soc/intel/cannonlake/exit_car_fsp.S
5 files changed, 168 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28581/1

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 4c4dfb2..9fe311e 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -53,6 +53,20 @@
 	  Display the user specified product data prior to memory
 	  initialization.
 
+config CPU_MICROCODE_CBFS_LEN
+	hex "Microcode update region length in bytes"
+	depends on FSP_CAR
+	default 0x0
+	help
+	  The length in bytes of the microcode update region.
+
+config CPU_MICROCODE_CBFS_LOC
+	hex "Microcode update base address in CBFS"
+	depends on FSP_CAR
+	default 0x0
+	help
+	  The location (base address) in CBFS that contains the microcode update binary.
+
 config FSP_T_CBFS
 	string "Name of FSP-T in CBFS"
 	depends on FSP_CAR
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index d5709ad..9d6b7db 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -52,6 +52,7 @@
 cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)
 $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
 $(CONFIG_FSP_T_CBFS)-type := fsp
+$(CONFIG_FSP_T_CBFS)-options := --xip
 
 cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
 $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 065d92b..01aed4f 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -21,6 +21,7 @@
 bootblock-y += lpc.c
 bootblock-y += p2sb.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
+bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_FSP.S
 
 romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
 romstage-y += gpio.c
@@ -69,6 +70,7 @@
 postcar-y += gspi.c
 postcar-y += spi.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
+postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
 verstage-y += gspi.c
 verstage-y += i2c.c
diff --git a/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S
new file mode 100644
index 0000000..bf75d1c
--- /dev/null
+++ b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
+
+#include <../../../arch/x86/walkcbfs.S>
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+.global cache_as_ram
+cache_as_ram:
+	post_code(0x21)
+
+	/* find fsp in cbfs */
+	lea fsp_name, %esi
+	mov $1f, %esp
+	jmp walkcbfs_asm
+
+1:
+	cmp   $0, %eax
+	jz    .halt_forever
+	mov   CBFS_FILE_OFFSET(%eax), %ebx
+	bswap %ebx
+	add   %eax,  %ebx
+	add   $0x94, %ebx
+
+	/*
+	 * ebx = FSP INFO HEADER
+	 * Calculate entry into FSP
+	 */
+	mov	0x30(%ebx), %eax	/* Load TempRamInitEntry */
+	add	0x1c(%ebx), %eax	/* add in the offset for FSP */
+
+	/*
+	 * Pass early init variables on a fake stack (no memory yet)
+	 * as well as the return location
+	 */
+	lea	CAR_init_stack, %esp
+
+	/* call FSP binary to setup temporary stack */
+	jmp	*%eax
+
+CAR_init_done:
+
+	/* Setup bootblock stack */
+	mov	%edx, %esp
+
+	/* clear CAR_GLOBAL area as it is not shared */
+	cld
+	xor     %eax, %eax
+	movl    $(_car_global_end), %ecx
+	movl    $(_car_global_start), %edi
+	sub     %edi, %ecx
+	rep     stosl
+	nop
+
+	/* We can call into C functions now */
+	call bootblock_c_entry
+
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever
+
+CAR_init_params:
+	.long   0x545F4450 /*CFLUPD_T*/
+	.long   0x554C4643 /*CFLUPD_T*/
+	.long   0x00000000
+	.long   0x00000000
+	.long   0x00000000
+	.long   0x00000000
+	.long   0x00000000
+	.long   0x00000000
+	.long	CONFIG_CPU_MICROCODE_CBFS_LOC		/* Microcode Location */
+	.long	CONFIG_CPU_MICROCODE_CBFS_LEN		/* Microcode Length */
+	.long	0xFFFFFFFF - CONFIG_ROM_SIZE + 1	/* Firmware Location */
+	.long	CONFIG_ROM_SIZE				/* Total Firmware Length */
+
+CAR_init_stack:
+	.long	CAR_init_done
+	.long	CAR_init_params
+
+fsp_name:
+	.ascii "fspt.bin\x00"
diff --git a/src/soc/intel/cannonlake/exit_car_fsp.S b/src/soc/intel/cannonlake/exit_car_fsp.S
new file mode 100644
index 0000000..e7457e0
--- /dev/null
+++ b/src/soc/intel/cannonlake/exit_car_fsp.S
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call.  More info can be found in the Apollo Lake FSP
+ * Integration Guide included with the FSP binary.  The below
+ * caching settings are based on an 8MiB Flash Size given as a
+ * parameter to TempRamInit.
+ *
+ * 	TempRamExit MTRR Settings:
+ * 	0x00000000  - 0x0009FFFF           | Write Back
+ * 	0x000C0000  - Top of Low Memory    | Write Back
+ * 	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
+ * 	0x100000000 - Top of High Memory   | Write Back
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+	/* Set up new stack. */
+	mov	post_car_stack_top, %esp
+
+	/* Call C code */
+	call	main

-- 
To view, visit https://review.coreboot.org/28581
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73
Gerrit-Change-Number: 28581
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180912/a51997b7/attachment-0001.html>

More information about the coreboot-gerrit mailing list