<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28581">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add FSP CAR Init support for CFL<br><br>FSP2.0 Driver supports TempRamInit & TempRamExit APIs to initialize<br>& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to<br>Coffeelake SoC when CONFIG_FSP_CAR is selected.<br><br>coffeelake CRB's RVP11 & RVP8 uses entire FSP including FSP-T to setup<br>CAR, MP init & MTRR programming without using coreboot Enhanced-NEM mode<br>and coreboot MP init.<br><br>BUG= None<br>TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.<br><br>Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73<br>Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/drivers/intel/fsp2_0/Kconfig<br>M src/drivers/intel/fsp2_0/Makefile.inc<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S<br>A src/soc/intel/cannonlake/exit_car_fsp.S<br>5 files changed, 168 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28581/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig</span><br><span>index 4c4dfb2..9fe311e 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/Kconfig</span><br><span>+++ b/src/drivers/intel/fsp2_0/Kconfig</span><br><span>@@ -53,6 +53,20 @@</span><br><span> Display the user specified product data prior to memory</span><br><span> initialization.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_MICROCODE_CBFS_LEN</span><br><span style="color: hsl(120, 100%, 40%);">+ hex "Microcode update region length in bytes"</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on FSP_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The length in bytes of the microcode update region.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_MICROCODE_CBFS_LOC</span><br><span style="color: hsl(120, 100%, 40%);">+ hex "Microcode update base address in CBFS"</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on FSP_CAR</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The location (base address) in CBFS that contains the microcode update binary.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config FSP_T_CBFS</span><br><span> string "Name of FSP-T in CBFS"</span><br><span> depends on FSP_CAR</span><br><span>diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc</span><br><span>index d5709ad..9d6b7db 100644</span><br><span>--- a/src/drivers/intel/fsp2_0/Makefile.inc</span><br><span>+++ b/src/drivers/intel/fsp2_0/Makefile.inc</span><br><span>@@ -52,6 +52,7 @@</span><br><span> cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)</span><br><span> $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))</span><br><span> $(CONFIG_FSP_T_CBFS)-type := fsp</span><br><span style="color: hsl(120, 100%, 40%);">+$(CONFIG_FSP_T_CBFS)-options := --xip</span><br><span> </span><br><span> cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)</span><br><span> $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 065d92b..01aed4f 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -21,6 +21,7 @@</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-y += p2sb.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_FSP.S</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c</span><br><span> romstage-y += gpio.c</span><br><span>@@ -69,6 +70,7 @@</span><br><span> postcar-y += gspi.c</span><br><span> postcar-y += spi.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S</span><br><span> </span><br><span> verstage-y += gspi.c</span><br><span> verstage-y += i2c.c</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S</span><br><span>new file mode 100644</span><br><span>index 0000000..bf75d1c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/cache_as_ram_FSP.S</span><br><span>@@ -0,0 +1,105 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <../../../arch/x86/walkcbfs.S></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global bootblock_pre_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock_pre_c_entry:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global cache_as_ram</span><br><span style="color: hsl(120, 100%, 40%);">+cache_as_ram:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x21)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* find fsp in cbfs */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea fsp_name, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $1f, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp walkcbfs_asm</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1:</span><br><span style="color: hsl(120, 100%, 40%);">+ cmp $0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jz .halt_forever</span><br><span style="color: hsl(120, 100%, 40%);">+ mov CBFS_FILE_OFFSET(%eax), %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ bswap %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ add %eax, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ add $0x94, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ebx = FSP INFO HEADER</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calculate entry into FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov 0x30(%ebx), %eax /* Load TempRamInitEntry */</span><br><span style="color: hsl(120, 100%, 40%);">+ add 0x1c(%ebx), %eax /* add in the offset for FSP */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pass early init variables on a fake stack (no memory yet)</span><br><span style="color: hsl(120, 100%, 40%);">+ * as well as the return location</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea CAR_init_stack, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* call FSP binary to setup temporary stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_done:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup bootblock stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %edx, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear CAR_GLOBAL area as it is not shared */</span><br><span style="color: hsl(120, 100%, 40%);">+ cld</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_end), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_start), %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ sub %edi, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span style="color: hsl(120, 100%, 40%);">+ nop</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We can call into C functions now */</span><br><span style="color: hsl(120, 100%, 40%);">+ call bootblock_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Never reached */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.halt_forever:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+ hlt</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .halt_forever</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_params:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x545F4450 /*CFLUPD_T*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x554C4643 /*CFLUPD_T*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_ROM_SIZE /* Total Firmware Length */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_stack:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_done</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_params</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+fsp_name:</span><br><span style="color: hsl(120, 100%, 40%);">+ .ascii "fspt.bin\x00"</span><br><span>diff --git a/src/soc/intel/cannonlake/exit_car_fsp.S b/src/soc/intel/cannonlake/exit_car_fsp.S</span><br><span>new file mode 100644</span><br><span>index 0000000..e7457e0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/exit_car_fsp.S</span><br><span>@@ -0,0 +1,46 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.</span><br><span style="color: hsl(120, 100%, 40%);">+ * This version of chipset_teardown_car sets up the stack, then bypasses</span><br><span style="color: hsl(120, 100%, 40%);">+ * the rest of arch/x86/exit_car.S and calls main() itself instead of</span><br><span style="color: hsl(120, 100%, 40%);">+ * returning to _start. In main(), the TempRamExit FSP API is called</span><br><span style="color: hsl(120, 100%, 40%);">+ * to tear down the CAR and set up caching which can be overwritten</span><br><span style="color: hsl(120, 100%, 40%);">+ * after the API call. More info can be found in the Apollo Lake FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ * Integration Guide included with the FSP binary. The below</span><br><span style="color: hsl(120, 100%, 40%);">+ * caching settings are based on an 8MiB Flash Size given as a</span><br><span style="color: hsl(120, 100%, 40%);">+ * parameter to TempRamInit.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * TempRamExit MTRR Settings:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.text</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up new stack. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov post_car_stack_top, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call C code */</span><br><span style="color: hsl(120, 100%, 40%);">+ call main</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28581">change 28581</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic17bc827e57df6ba0b891f906c7adac1bb5d4d73 </div>
<div style="display:none"> Gerrit-Change-Number: 28581 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>