[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy: Set UPD CmdTriStateDis for rammus
Marx Wang (Code Review)
gerrit at coreboot.org
Tue Sep 11 06:12:05 CEST 2018
Marx Wang has uploaded this change for review. ( https://review.coreboot.org/28568
Change subject: mb/google/poppy: Set UPD CmdTriStateDis for rammus
......................................................................
mb/google/poppy: Set UPD CmdTriStateDis for rammus
This patch sets the MRC UPD CmdTriStateDis for the
rammus boards. Rammus is LPDDR3 design without RTT
for CMD/CTRL
BUG=none
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: marxwang <marx.wang at intel.com>
---
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28568/1
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 7c1b02f..f94b30d 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -27,6 +27,9 @@
# Enable S0ix
register "s0ix_enable" = "1"
+ # Disable Command TriState
+ register "CmdTriStateDis" = "1"
+
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Gerrit-Change-Number: 28568
Gerrit-PatchSet: 1
Gerrit-Owner: Marx Wang <marx.wang at intel.com>
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