[coreboot-gerrit] Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28096 )

Change subject: riscv: add support for supervisor binary interface (SBI)
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Patch Set 29:

(1 comment)

https://review.coreboot.org/#/c/28096/29/src/arch/riscv/include/mcall.h
File src/arch/riscv/include/mcall.h:

https://review.coreboot.org/#/c/28096/29/src/arch/riscv/include/mcall.h@66
PS29, Line 66:  * MISP needs to be mapped to memory space, it does not define how to map. 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Gerrit-Change-Number: 28096
Gerrit-PatchSet: 29
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Philipp Hug <philipp at hug.cx>
Gerrit-Reviewer: Ronald G. Minnich <rminnich at gmail.com>
Gerrit-Reviewer: Shawn Chang <citypw at gmail.com>
Gerrit-Reviewer: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Reviewer: ron minnich (1001188)
Gerrit-Comment-Date: Fri, 07 Sep 2018 14:17:16 +0000
Gerrit-HasComments: Yes
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