[coreboot-gerrit] Change in coreboot[master]: mb/google/sarien: Enable Wilco EC
Duncan Laurie (Code Review)
gerrit at coreboot.org
Wed Oct 31 21:52:19 CET 2018
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29411
Change subject: mb/google/sarien: Enable Wilco EC
......................................................................
mb/google/sarien: Enable Wilco EC
The Sarien mainboard uses the newly added Wilco EC.
- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup
Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
M src/mainboard/google/sarien/Kconfig
M src/mainboard/google/sarien/Makefile.inc
M src/mainboard/google/sarien/bootblock.c
M src/mainboard/google/sarien/dsdt.asl
A src/mainboard/google/sarien/smihandler.c
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
A src/mainboard/google/sarien/variants/arcada/include/variant/ec.h
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
A src/mainboard/google/sarien/variants/sarien/include/variant/ec.h
9 files changed, 135 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29411/1
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index ac1afd5..fcf9f44 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -6,6 +6,7 @@
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
select DRIVERS_PS2_KEYBOARD
+ select EC_GOOGLE_WILCO
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc
index d0b1cef..3370900 100644
--- a/src/mainboard/google/sarien/Makefile.inc
+++ b/src/mainboard/google/sarien/Makefile.inc
@@ -19,6 +19,8 @@
romstage-y += romstage.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c
index 399a127..bee9b1a 100644
--- a/src/mainboard/google/sarien/bootblock.c
+++ b/src/mainboard/google/sarien/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <bootblock_common.h>
+#include <ec/google/wilco/bootblock.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
@@ -29,4 +30,5 @@
void bootblock_mainboard_init(void)
{
early_config_gpio();
+ wilco_ec_early_init();
}
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 3295078..26efdb7 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
+#include "variant/ec.h"
+
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -50,4 +52,15 @@
/* Chipset specific sleep states */
#include <soc/intel/cannonlake/acpi/sleepstates.asl>
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO)
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/wilco/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/wilco/acpi/ec.asl>
+ }
+#endif
}
diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c
new file mode 100644
index 0000000..0efcaa9
--- /dev/null
+++ b/src/mainboard/google/sarien/smihandler.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/wilco/smm.h>
+#include <soc/smm.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ wilco_ec_smi_espi();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ wilco_ec_smi_sleep(slp_typ);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ wilco_ec_smi_apmc(apmc);
+ return 0;
+}
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 939acd2..e3b9680 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -8,6 +8,11 @@
register "gpe0_dw1" = "PMC_GPP_C"
register "gpe0_dw2" = "PMC_GPP_D"
+ # EC host command ranges
+ register "gen1_dec" = "0x00040931" # 0x930-0x937
+ register "gen2_dec" = "0x00040941" # 0x940-0x947
+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f
+
# FSP configuration
register "SaGv" = "3"
register "HeciEnabled" = "1"
@@ -152,7 +157,11 @@
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC/eSPI
+ device pci 1f.0 on
+ chip ec/google/wilco
+ device pnp 0c09.0 on end
+ end
+ end # LPC/eSPI
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h
new file mode 100644
index 0000000..cb73092
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC wake pin */
+#define EC_WAKE_PIN GPE0_DW1_12
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* Enable PS/2 keyboard */
+#define SIO_EC_ENABLE_PS2K
+
+#endif
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 1f262bf..1360b3f 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -8,6 +8,11 @@
register "gpe0_dw1" = "PMC_GPP_C"
register "gpe0_dw2" = "PMC_GPP_D"
+ # EC host command ranges
+ register "gen1_dec" = "0x00040931" # 0x930-0x937
+ register "gen2_dec" = "0x00040941" # 0x940-0x947
+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f
+
# FSP configuration
register "SaGv" = "3"
register "HeciEnabled" = "1"
@@ -152,7 +157,11 @@
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC/eSPI
+ device pci 1f.0 on
+ chip ec/google/wilco
+ device pnp 0c09.0 on end
+ end
+ end # LPC/eSPI
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h
new file mode 100644
index 0000000..cb73092
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC wake pin */
+#define EC_WAKE_PIN GPE0_DW1_12
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* Enable PS/2 keyboard */
+#define SIO_EC_ENABLE_PS2K
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Gerrit-Change-Number: 29411
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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