<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29411">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Enable Wilco EC<br><br>The Sarien mainboard uses the newly added Wilco EC.<br><br>- enable CONFIG_EC_GOOGLE_WILCO<br>- add the device and host command ranges to the devicetree<br>- have the mainboard SMI handlers call the EC handlers<br>- add EC and SuperIO devices to the ACPI DSDT<br>- call the early init hook for serial setup<br><br>Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619<br>Signed-off-by: Duncan Laurie <dlaurie@google.com><br>---<br>M src/mainboard/google/sarien/Kconfig<br>M src/mainboard/google/sarien/Makefile.inc<br>M src/mainboard/google/sarien/bootblock.c<br>M src/mainboard/google/sarien/dsdt.asl<br>A src/mainboard/google/sarien/smihandler.c<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>A src/mainboard/google/sarien/variants/arcada/include/variant/ec.h<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>A src/mainboard/google/sarien/variants/sarien/include/variant/ec.h<br>9 files changed, 135 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29411/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig</span><br><span>index ac1afd5..fcf9f44 100644</span><br><span>--- a/src/mainboard/google/sarien/Kconfig</span><br><span>+++ b/src/mainboard/google/sarien/Kconfig</span><br><span>@@ -6,6 +6,7 @@</span><br><span> select DRIVERS_I2C_HID</span><br><span> select DRIVERS_SPI_ACPI</span><br><span> select DRIVERS_PS2_KEYBOARD</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_GOOGLE_WILCO</span><br><span> select GENERIC_SPD_BIN</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span>diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc</span><br><span>index d0b1cef..3370900 100644</span><br><span>--- a/src/mainboard/google/sarien/Makefile.inc</span><br><span>+++ b/src/mainboard/google/sarien/Makefile.inc</span><br><span>@@ -19,6 +19,8 @@</span><br><span> </span><br><span> romstage-y += romstage.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> bootblock-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span> ramstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span> romstage-$(CONFIG_CHROMEOS) += chromeos.c</span><br><span>diff --git a/src/mainboard/google/sarien/bootblock.c b/src/mainboard/google/sarien/bootblock.c</span><br><span>index 399a127..bee9b1a 100644</span><br><span>--- a/src/mainboard/google/sarien/bootblock.c</span><br><span>+++ b/src/mainboard/google/sarien/bootblock.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/wilco/bootblock.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <variant/gpio.h></span><br><span> </span><br><span>@@ -29,4 +30,5 @@</span><br><span> void bootblock_mainboard_init(void)</span><br><span> {</span><br><span> early_config_gpio();</span><br><span style="color: hsl(120, 100%, 40%);">+ wilco_ec_early_init();</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl</span><br><span>index 3295078..26efdb7 100644</span><br><span>--- a/src/mainboard/google/sarien/dsdt.asl</span><br><span>+++ b/src/mainboard/google/sarien/dsdt.asl</span><br><span>@@ -13,6 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include "variant/ec.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> DefinitionBlock(</span><br><span> "dsdt.aml",</span><br><span> "DSDT",</span><br><span>@@ -50,4 +52,15 @@</span><br><span> </span><br><span> /* Chipset specific sleep states */</span><br><span> #include <soc/intel/cannonlake/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chrome OS Embedded Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB.PCI0.LPCB)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC SuperIO functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/wilco/acpi/superio.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* ACPI code for EC functions */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <ec/google/wilco/acpi/ec.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/sarien/smihandler.c b/src/mainboard/google/sarien/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0efcaa9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/smihandler.c</span><br><span>@@ -0,0 +1,35 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/wilco/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_espi_handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ wilco_ec_smi_espi();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ wilco_ec_smi_sleep(slp_typ);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_smi_apmc(u8 apmc)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ wilco_ec_smi_apmc(apmc);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index 939acd2..e3b9680 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -8,6 +8,11 @@</span><br><span> register "gpe0_dw1" = "PMC_GPP_C"</span><br><span> register "gpe0_dw2" = "PMC_GPP_D"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00040931" # 0x930-0x937</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x00040941" # 0x940-0x947</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "HeciEnabled" = "1"</span><br><span>@@ -152,7 +157,11 @@</span><br><span> device pci 1e.1 off end # UART #1</span><br><span> device pci 1e.2 off end # GSPI #0</span><br><span> device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on end # LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/wilco</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC/eSPI</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span> device pci 1f.3 on end # Intel HDA</span><br><span>diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cb73092</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef VARIANT_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define VARIANT_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_WAKE_PIN GPE0_DW1_12</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* eSPI virtual wire reporting */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_ESPI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable PS/2 keyboard */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_ENABLE_PS2K</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index 1f262bf..1360b3f 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -8,6 +8,11 @@</span><br><span> register "gpe0_dw1" = "PMC_GPP_C"</span><br><span> register "gpe0_dw2" = "PMC_GPP_D"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00040931" # 0x930-0x937</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x00040941" # 0x940-0x947</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x000c0951" # 0x950-0x95f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # FSP configuration</span><br><span> register "SaGv" = "3"</span><br><span> register "HeciEnabled" = "1"</span><br><span>@@ -152,7 +157,11 @@</span><br><span> device pci 1e.1 off end # UART #1</span><br><span> device pci 1e.2 off end # GSPI #0</span><br><span> device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 on end # LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/wilco</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC/eSPI</span><br><span> device pci 1f.1 on end # P2SB</span><br><span> device pci 1f.2 on end # Power Management Controller</span><br><span> device pci 1f.3 on end # Intel HDA</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cb73092</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef VARIANT_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define VARIANT_EC_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_WAKE_PIN GPE0_DW1_12</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* eSPI virtual wire reporting */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_ESPI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable PS/2 keyboard */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_ENABLE_PS2K</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29411">change 29411</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29411"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 </div>
<div style="display:none"> Gerrit-Change-Number: 29411 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>