[coreboot-gerrit] Change in coreboot[master]: src: Add missing include <stdint.h>

Elyes HAOUAS (Code Review) gerrit at coreboot.org
Wed Oct 31 18:31:37 CET 2018 

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29403


Change subject: src: Add missing include <stdint.h>
......................................................................

src: Add missing include <stdint.h>

This is part #2 follows Change-Id: I6a9d71e69

Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/common/common.h
M src/cpu/intel/haswell/chip.h
M src/device/oprom/yabel/compat/time.h
M src/drivers/pc80/tpm/chip.h
M src/ec/smsc/mec1308/chip.h
M src/include/device/path.h
M src/include/device/pcix.h
M src/mainboard/google/parrot/ec.h
M src/mainboard/roda/rk886ex/m3885.h
M src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
M src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
M src/mainboard/siemens/mc_tcu3/lcd_panel.h
M src/northbridge/amd/agesa/family14/chip.h
M src/northbridge/amd/agesa/family15tn/chip.h
M src/northbridge/amd/agesa/family16kb/chip.h
M src/northbridge/amd/amdfam10/northbridge.h
M src/northbridge/amd/amdht/AsPsNb.h
M src/northbridge/amd/pi/00630F01/chip.h
M src/northbridge/amd/pi/00660F01/chip.h
M src/northbridge/amd/pi/00730F01/chip.h
M src/northbridge/intel/pineview/raminit.h
M src/northbridge/intel/x4x/iomap.h
M src/soc/cavium/common/pci/chip.h
M src/soc/intel/broadwell/include/soc/xhci.h
M src/soc/nvidia/tegra210/include/soc/display.h
M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h
M src/soc/rockchip/common/include/soc/pwm.h
M src/soc/rockchip/rk3288/include/soc/display.h
M src/soc/rockchip/rk3399/include/soc/saradc.h
M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h
M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
M src/southbridge/amd/agesa/hudson/chip.h
M src/southbridge/amd/cimx/sb800/sb_cimx.h
M src/southbridge/amd/cimx/sb900/sb_cimx.h
M src/southbridge/amd/sb700/chip.h
M src/southbridge/intel/common/pciehp.h
M src/superio/fintek/f81216h/f81216h.h
M src/superio/nuvoton/nct5104d/chip.h
M src/superio/serverengines/pilot/pilot.h
M src/superio/smsc/lpc47n227/lpc47n227.h
40 files changed, 84 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/1

diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index 81c9f16..1c0ffee 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -15,6 +15,8 @@
 #ifndef _CPU_INTEL_COMMON_H
 #define _CPU_INTEL_COMMON_H
 
+#include <stdint.h>
+
 void set_vmx(void);
 
 /*
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index cd9ec5d..af8b54e 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <stdint.h>
+
 extern struct chip_operations cpu_intel_haswell_ops;
 
 /* Magic value used to locate this chip in the device tree */
diff --git a/src/device/oprom/yabel/compat/time.h b/src/device/oprom/yabel/compat/time.h
index 1cbbdca..dd5db9c 100644
--- a/src/device/oprom/yabel/compat/time.h
+++ b/src/device/oprom/yabel/compat/time.h
@@ -34,6 +34,8 @@
 #ifndef _BIOSEMU_COMPAT_TIME_H
 #define _BIOSEMU_COMPAT_TIME_H
 
+#include <stdint.h>
+
 /* TODO: check how this works in x86 */
 extern unsigned long tb_freq;
 u64 get_time(void);
diff --git a/src/drivers/pc80/tpm/chip.h b/src/drivers/pc80/tpm/chip.h
index b13d23c..ac888e6 100644
--- a/src/drivers/pc80/tpm/chip.h
+++ b/src/drivers/pc80/tpm/chip.h
@@ -16,6 +16,8 @@
 #ifndef DRIVERS_PC80_TPM_CHIP_H
 #define DRIVERS_PC80_TPM_CHIP_H
 
+#include <stdint.h>
+
 typedef struct drivers_pc80_tpm_config {
 	/*
 	 * TPM Interrupt polarity:
diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h
index 8df043c..3c997fd 100644
--- a/src/ec/smsc/mec1308/chip.h
+++ b/src/ec/smsc/mec1308/chip.h
@@ -17,6 +17,8 @@
 #ifndef _EC_SMSC_MEC1308_CHIP_H
 #define _EC_SMSC_MEC1308_CHIP_H
 
+#include <stdint.h>
+
 struct ec_smsc_mec1308_config
 {
 	u16 mailbox_port;
diff --git a/src/include/device/path.h b/src/include/device/path.h
index 0d9c681..6736bed 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -1,6 +1,8 @@
 #ifndef DEVICE_PATH_H
 #define DEVICE_PATH_H
 
+#include <stdint.h>
+
 enum device_path_type {
 	DEVICE_PATH_NONE = 0,
 	DEVICE_PATH_ROOT,
diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h
index ca482d2..fb0d3bb 100644
--- a/src/include/device/pcix.h
+++ b/src/include/device/pcix.h
@@ -2,6 +2,8 @@
 #define DEVICE_PCIX_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+#include <stdint.h>
+
 void pcix_scan_bridge(struct device *dev);
 
 const char *pcix_speed(u16 sstatus);
diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h
index e389a77..0df9de7 100644
--- a/src/mainboard/google/parrot/ec.h
+++ b/src/mainboard/google/parrot/ec.h
@@ -54,6 +54,8 @@
  */
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 extern void parrot_ec_init(void);
 u8 parrot_rev(void);
 int parrot_ec_running_ro(void);
diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h
index d2dcb14..1f93d1e 100644
--- a/src/mainboard/roda/rk886ex/m3885.h
+++ b/src/mainboard/roda/rk886ex/m3885.h
@@ -16,6 +16,8 @@
 #ifndef _MAINBOARD_M3885_H
 #define _MAINBOARD_M3885_H
 
+#include <stdint.h>
+
 #define M3885_CMCMD		0x04
 #define M3885_CMDAT1		0x05
 #define M3885_CMDAT2		0x06
diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
index e80edc5..48e6af4 100644
--- a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
+++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <stdint.h>
+
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0262,	/* Codec Vendor / Device ID: Realtek ALC262 */
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
index edc5f64..ec4e4fc 100644
--- a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <stdint.h>
+
 const u32 cim_verb_data[] = {
 	/* coreboot specific header */
 	0x10ec0262,	/* Codec Vendor / Device ID: Realtek ALC262 */
diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.h b/src/mainboard/siemens/mc_tcu3/lcd_panel.h
index a27cc52..377a066 100644
--- a/src/mainboard/siemens/mc_tcu3/lcd_panel.h
+++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.h
@@ -16,6 +16,8 @@
 #ifndef _LCD_PANEL_H_
 #define _LCD_PANEL_H_
 
+#include <stdint.h>
+
 /* This GPIOs are used for LCD panel type encoding */
 #define LCD_TYPE_GPIO_BIT0	40
 #define LCD_TYPE_GPIO_BIT1	41
diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
index 211ee24..e9a13ea 100644
--- a/src/northbridge/amd/agesa/family14/chip.h
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -16,6 +16,8 @@
 #ifndef _NB_AGESA_CHIP_H_
 #define _NB_AGESA_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_agesa_family14_config
 {
 	/*
diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h
index a520708..1df2d82 100644
--- a/src/northbridge/amd/agesa/family15tn/chip.h
+++ b/src/northbridge/amd/agesa/family15tn/chip.h
@@ -16,6 +16,8 @@
 #ifndef _NB_AGESA_CHIP_H_
 #define _NB_AGESA_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_agesa_family15tn_config
 {
 	u8 spdAddrLookup[2][2][4];
diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h
index 37b5cc1..1fed152 100644
--- a/src/northbridge/amd/agesa/family16kb/chip.h
+++ b/src/northbridge/amd/agesa/family16kb/chip.h
@@ -16,6 +16,8 @@
 #ifndef _NB_AGESA_CHIP_H_
 #define _NB_AGESA_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_agesa_family16kb_config
 {
 	u8 spdAddrLookup[2][2][4];
diff --git a/src/northbridge/amd/amdfam10/northbridge.h b/src/northbridge/amd/amdfam10/northbridge.h
index 69d7415..349becb 100644
--- a/src/northbridge/amd/amdfam10/northbridge.h
+++ b/src/northbridge/amd/amdfam10/northbridge.h
@@ -16,6 +16,8 @@
 #ifndef NORTHBRIDGE_AMD_AMDFAM10_H
 #define NORTHBRIDGE_AMD_AMDFAM10_H
 
+#include <stdint.h>
+
 u32 amdfam10_scan_root_bus(struct device *root, u32 max);
 void get_pci1234(void);
 
diff --git a/src/northbridge/amd/amdht/AsPsNb.h b/src/northbridge/amd/amdht/AsPsNb.h
index 3500892..b90598d 100644
--- a/src/northbridge/amd/amdht/AsPsNb.h
+++ b/src/northbridge/amd/amdht/AsPsNb.h
@@ -13,10 +13,11 @@
  * GNU General Public License for more details.
  */
 
-
 #ifndef ASPSNB_H
 #define ASPSNB_H
 
+#include <stdint.h>
+
 u8 getMinNbCOF(void);
 
 #endif
diff --git a/src/northbridge/amd/pi/00630F01/chip.h b/src/northbridge/amd/pi/00630F01/chip.h
index 35b4a57..3032c30 100644
--- a/src/northbridge/amd/pi/00630F01/chip.h
+++ b/src/northbridge/amd/pi/00630F01/chip.h
@@ -16,6 +16,8 @@
 #ifndef _AGESA_00630F01_CHIP_H_
 #define _AGESA_00630F01_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_pi_00630F01_config
 {
 	u8 spdAddrLookup[1][2][2];
diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h
index ab0e3d2..f9614ca 100644
--- a/src/northbridge/amd/pi/00660F01/chip.h
+++ b/src/northbridge/amd/pi/00660F01/chip.h
@@ -16,6 +16,8 @@
 #ifndef _PI_FAM15CZ_CHIP_H_
 #define _PI_FAM15CZ_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_pi_00660F01_config
 {
 	u8 spdAddrLookup[2][2][4];
diff --git a/src/northbridge/amd/pi/00730F01/chip.h b/src/northbridge/amd/pi/00730F01/chip.h
index 3db79d4..99754eb 100644
--- a/src/northbridge/amd/pi/00730F01/chip.h
+++ b/src/northbridge/amd/pi/00730F01/chip.h
@@ -16,6 +16,8 @@
 #ifndef _PI_00730F01_CHIP_H_
 #define _PI_00730F01_CHIP_H_
 
+#include <stdint.h>
+
 struct northbridge_amd_pi_00730F01_config
 {
 	u8 spdAddrLookup[1][1][2];
diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h
index dc8de74..60133f4 100644
--- a/src/northbridge/intel/pineview/raminit.h
+++ b/src/northbridge/intel/pineview/raminit.h
@@ -17,6 +17,8 @@
 #ifndef PINEVIEW_RAMINIT_H
 #define PINEVIEW_RAMINIT_H
 
+#include <stdint.h>
+
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
 
 #endif /* PINEVIEW_RAMINIT_H */
diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h
index db608c5..debb1aa 100644
--- a/src/northbridge/intel/x4x/iomap.h
+++ b/src/northbridge/intel/x4x/iomap.h
@@ -17,6 +17,8 @@
 #ifndef X4X_IOMAP_H
 #define X4X_IOMAP_H
 
+#include <stdint.h>
+
 /* 4 KB per PCIe device */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
 
diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h
index 0d0d33f..ccc1551 100644
--- a/src/soc/cavium/common/pci/chip.h
+++ b/src/soc/cavium/common/pci/chip.h
@@ -16,6 +16,8 @@
 #ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H
 #define __SOC_CAVIUM_COMMON_PCI_CHIP_H
 
+#include <stdint.h>
+
 struct soc_cavium_common_pci_config {
 	/**
 	 * Mark the PCI device as secure.
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index 33e4c2d..4e172f3 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -51,6 +51,7 @@
 #define   XHCI_PLSW_ENABLE	(5 << 5)	/* Transition from disabled */
 
 #ifdef __SMM__
+#include <stdint.h>
 void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 #endif
 
diff --git a/src/soc/nvidia/tegra210/include/soc/display.h b/src/soc/nvidia/tegra210/include/soc/display.h
index 74c289e..86750c9 100644
--- a/src/soc/nvidia/tegra210/include/soc/display.h
+++ b/src/soc/nvidia/tegra210/include/soc/display.h
@@ -16,6 +16,8 @@
 #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__
 #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__
 
+#include <stdint.h>
+
 #define COLOR_WHITE	0xFFFFFF
 #define COLOR_BLACK	0x000000
 
diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h
index dbaaa22..245385f 100644
--- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h
+++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h
@@ -15,6 +15,8 @@
 #ifndef __TEGRA_DSI_H__
 #define __TEGRA_DSI_H__
 
+#include <stdint.h>
+
 #define DSI_INCR_SYNCPT			0x00
 #define DSI_INCR_SYNCPT_CONTROL		0x01
 #define DSI_INCR_SYNCPT_ERROR		0x02
diff --git a/src/soc/rockchip/common/include/soc/pwm.h b/src/soc/rockchip/common/include/soc/pwm.h
index 4b4b2c0..90f077c 100644
--- a/src/soc/rockchip/common/include/soc/pwm.h
+++ b/src/soc/rockchip/common/include/soc/pwm.h
@@ -16,6 +16,8 @@
 #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H
 #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H
 
+#include <stdint.h>
+
 void pwm_init(u32 id, u32 period_ns, u32 duty_ns);
 
 #endif  /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H */
diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h
index 8ffa922..cc76629 100644
--- a/src/soc/rockchip/rk3288/include/soc/display.h
+++ b/src/soc/rockchip/rk3288/include/soc/display.h
@@ -16,6 +16,8 @@
 #ifndef __SOC_ROCKCHIP_RK3288_DISPLAY_H__
 #define __SOC_ROCKCHIP_RK3288_DISPLAY_H__
 
+#include <stdint.h>
+
 /*
  * this bit select edp phy pll, this bit define different between
  * rk3288 and rk3399 in edp phy, so implement it in soc specific code
diff --git a/src/soc/rockchip/rk3399/include/soc/saradc.h b/src/soc/rockchip/rk3399/include/soc/saradc.h
index 90f743e..69118b5 100644
--- a/src/soc/rockchip/rk3399/include/soc/saradc.h
+++ b/src/soc/rockchip/rk3399/include/soc/saradc.h
@@ -17,5 +17,7 @@
 #ifndef __SOC_ROCKCHIP_RK3399_SARADC_H__
 #define __SOC_ROCKCHIP_RK3399_SARADC_H__
 
+#include <stdint.h>
+
 u32 get_saradc_value(u32 chn);
 #endif
diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h
index 0833934..635a9bb 100644
--- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h
+++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h
@@ -16,6 +16,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
 #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
 
+#include <stdint.h>
+
 /* These are pointers to function pointers. Double indirection! */
 static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;
 static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;
diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
index 40af40b..2c8cef0 100644
--- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
+++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
@@ -16,6 +16,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
 #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
 
+#include <stdint.h>
+
 /* These are pointers to function pointers. Double indirection! */
 static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;
 static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;
diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h
index 873d7fb..27d6dfb 100644
--- a/src/southbridge/amd/agesa/hudson/chip.h
+++ b/src/southbridge/amd/agesa/hudson/chip.h
@@ -16,6 +16,8 @@
 #ifndef HUDSON_CHIP_H
 #define HUDSON_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_amd_agesa_hudson_config
 {
 	u8  sd_mode;
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 16ac6fe..70b3e4f 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -17,6 +17,8 @@
 #ifndef _CIMX_H_
 #define _CIMX_H_
 
+#include <stdint.h>
+
 /**
  * AMD South Bridge CIMx entry point wrapper
  */
diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h
index 99b246e..1746050 100644
--- a/src/southbridge/amd/cimx/sb900/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h
@@ -17,6 +17,8 @@
 #ifndef _CIMX_SB_EARLY_H_
 #define _CIMX_SB_EARLY_H_
 
+#include <stdint.h>
+
 #define PM_INDEX	0xcd6
 #define PM_DATA		0xcd7
 
diff --git a/src/southbridge/amd/sb700/chip.h b/src/southbridge/amd/sb700/chip.h
index fe3289d..13ff48a 100644
--- a/src/southbridge/amd/sb700/chip.h
+++ b/src/southbridge/amd/sb700/chip.h
@@ -16,6 +16,8 @@
 #ifndef SB700_CHIP_H
 #define SB700_CHIP_H
 
+#include <stdint.h>
+
 struct southbridge_amd_sb700_config
 {
 	u32 boot_switch_sata_ide : 1;
diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h
index 7bf47f3..7153798 100644
--- a/src/southbridge/intel/common/pciehp.h
+++ b/src/southbridge/intel/common/pciehp.h
@@ -1,2 +1,9 @@
+#ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEPH_H
+#define SOUTHBRIDGE_INTEL_COMMON_PCIEPH_H
+
+#include <stdint.h>
+
 void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);
 void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
+
+#endif
diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h
index ec54165..8da1379 100644
--- a/src/superio/fintek/f81216h/f81216h.h
+++ b/src/superio/fintek/f81216h/f81216h.h
@@ -17,6 +17,8 @@
 #ifndef SUPERIO_FINTEK_F81216H_H
 #define SUPERIO_FINTEK_F81216H_H
 
+#include <stdint.h>
+
 /* Logical Device Numbers (LDN). */
 #define F81216H_SP1    0x00	/* UART1 (+CIR mode) */
 #define F81216H_SP2    0x01	/* UART2 */
diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h
index d351053..a35fb3c 100644
--- a/src/superio/nuvoton/nct5104d/chip.h
+++ b/src/superio/nuvoton/nct5104d/chip.h
@@ -17,6 +17,8 @@
 #ifndef SUPERIO_NUVOTON_NCT5104D_CHIP_H
 #define SUPERIO_NUVOTON_NCT5104D_CHIP_H
 
+#include <stdint.h>
+
 struct superio_nuvoton_nct5104d_config {
 	u8 irq_trigger_type;
 };
diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h
index ab9b9c8..c3dfd02 100644
--- a/src/superio/serverengines/pilot/pilot.h
+++ b/src/superio/serverengines/pilot/pilot.h
@@ -18,6 +18,8 @@
 #ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H
 #define SUPERIO_SERVERENGINES_PILOT_PILOT_H
 
+#include <stdint.h>
+
 /* PILOT Super I/O is only based on LPC observation done on factory system. */
 
 #define PILOT_LD1 0x01 /* Logical device 1 */
diff --git a/src/superio/smsc/lpc47n227/lpc47n227.h b/src/superio/smsc/lpc47n227/lpc47n227.h
index d629a67..8d958f1 100644
--- a/src/superio/smsc/lpc47n227/lpc47n227.h
+++ b/src/superio/smsc/lpc47n227/lpc47n227.h
@@ -16,6 +16,8 @@
 #ifndef SUPERIO_SMSC_LPC47N227_LPC47N227_H
 #define SUPERIO_SMSC_LPC47N227_LPC47N227_H
 
+#include <stdint.h>
+
 /*
  * Since the LPC47N227 does not have logical devices but a flat configuration
  * space, these are arbitrary, but must match declarations in the mainboard

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
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Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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