<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29403">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Add missing include <stdint.h><br><br>This is part #2 follows Change-Id: I6a9d71e69<br><br>Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/common/common.h<br>M src/cpu/intel/haswell/chip.h<br>M src/device/oprom/yabel/compat/time.h<br>M src/drivers/pc80/tpm/chip.h<br>M src/ec/smsc/mec1308/chip.h<br>M src/include/device/path.h<br>M src/include/device/pcix.h<br>M src/mainboard/google/parrot/ec.h<br>M src/mainboard/roda/rk886ex/m3885.h<br>M src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h<br>M src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h<br>M src/mainboard/siemens/mc_tcu3/lcd_panel.h<br>M src/northbridge/amd/agesa/family14/chip.h<br>M src/northbridge/amd/agesa/family15tn/chip.h<br>M src/northbridge/amd/agesa/family16kb/chip.h<br>M src/northbridge/amd/amdfam10/northbridge.h<br>M src/northbridge/amd/amdht/AsPsNb.h<br>M src/northbridge/amd/pi/00630F01/chip.h<br>M src/northbridge/amd/pi/00660F01/chip.h<br>M src/northbridge/amd/pi/00730F01/chip.h<br>M src/northbridge/intel/pineview/raminit.h<br>M src/northbridge/intel/x4x/iomap.h<br>M src/soc/cavium/common/pci/chip.h<br>M src/soc/intel/broadwell/include/soc/xhci.h<br>M src/soc/nvidia/tegra210/include/soc/display.h<br>M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h<br>M src/soc/rockchip/common/include/soc/pwm.h<br>M src/soc/rockchip/rk3288/include/soc/display.h<br>M src/soc/rockchip/rk3399/include/soc/saradc.h<br>M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h<br>M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h<br>M src/southbridge/amd/agesa/hudson/chip.h<br>M src/southbridge/amd/cimx/sb800/sb_cimx.h<br>M src/southbridge/amd/cimx/sb900/sb_cimx.h<br>M src/southbridge/amd/sb700/chip.h<br>M src/southbridge/intel/common/pciehp.h<br>M src/superio/fintek/f81216h/f81216h.h<br>M src/superio/nuvoton/nct5104d/chip.h<br>M src/superio/serverengines/pilot/pilot.h<br>M src/superio/smsc/lpc47n227/lpc47n227.h<br>40 files changed, 84 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h</span><br><span>index 81c9f16..1c0ffee 100644</span><br><span>--- a/src/cpu/intel/common/common.h</span><br><span>+++ b/src/cpu/intel/common/common.h</span><br><span>@@ -15,6 +15,8 @@</span><br><span> #ifndef _CPU_INTEL_COMMON_H</span><br><span> #define _CPU_INTEL_COMMON_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void set_vmx(void);</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h</span><br><span>index cd9ec5d..af8b54e 100644</span><br><span>--- a/src/cpu/intel/haswell/chip.h</span><br><span>+++ b/src/cpu/intel/haswell/chip.h</span><br><span>@@ -13,6 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> extern struct chip_operations cpu_intel_haswell_ops;</span><br><span> </span><br><span> /* Magic value used to locate this chip in the device tree */</span><br><span>diff --git a/src/device/oprom/yabel/compat/time.h b/src/device/oprom/yabel/compat/time.h</span><br><span>index 1cbbdca..dd5db9c 100644</span><br><span>--- a/src/device/oprom/yabel/compat/time.h</span><br><span>+++ b/src/device/oprom/yabel/compat/time.h</span><br><span>@@ -34,6 +34,8 @@</span><br><span> #ifndef _BIOSEMU_COMPAT_TIME_H</span><br><span> #define _BIOSEMU_COMPAT_TIME_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* TODO: check how this works in x86 */</span><br><span> extern unsigned long tb_freq;</span><br><span> u64 get_time(void);</span><br><span>diff --git a/src/drivers/pc80/tpm/chip.h b/src/drivers/pc80/tpm/chip.h</span><br><span>index b13d23c..ac888e6 100644</span><br><span>--- a/src/drivers/pc80/tpm/chip.h</span><br><span>+++ b/src/drivers/pc80/tpm/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef DRIVERS_PC80_TPM_CHIP_H</span><br><span> #define DRIVERS_PC80_TPM_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef struct drivers_pc80_tpm_config {</span><br><span> /*</span><br><span> * TPM Interrupt polarity:</span><br><span>diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h</span><br><span>index 8df043c..3c997fd 100644</span><br><span>--- a/src/ec/smsc/mec1308/chip.h</span><br><span>+++ b/src/ec/smsc/mec1308/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef _EC_SMSC_MEC1308_CHIP_H</span><br><span> #define _EC_SMSC_MEC1308_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct ec_smsc_mec1308_config</span><br><span> {</span><br><span> u16 mailbox_port;</span><br><span>diff --git a/src/include/device/path.h b/src/include/device/path.h</span><br><span>index 0d9c681..6736bed 100644</span><br><span>--- a/src/include/device/path.h</span><br><span>+++ b/src/include/device/path.h</span><br><span>@@ -1,6 +1,8 @@</span><br><span> #ifndef DEVICE_PATH_H</span><br><span> #define DEVICE_PATH_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum device_path_type {</span><br><span> DEVICE_PATH_NONE = 0,</span><br><span> DEVICE_PATH_ROOT,</span><br><span>diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h</span><br><span>index ca482d2..fb0d3bb 100644</span><br><span>--- a/src/include/device/pcix.h</span><br><span>+++ b/src/include/device/pcix.h</span><br><span>@@ -2,6 +2,8 @@</span><br><span> #define DEVICE_PCIX_H</span><br><span> /* (c) 2005 Linux Networx GPL see COPYING for details */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pcix_scan_bridge(struct device *dev);</span><br><span> </span><br><span> const char *pcix_speed(u16 sstatus);</span><br><span>diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h</span><br><span>index e389a77..0df9de7 100644</span><br><span>--- a/src/mainboard/google/parrot/ec.h</span><br><span>+++ b/src/mainboard/google/parrot/ec.h</span><br><span>@@ -54,6 +54,8 @@</span><br><span> */</span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> extern void parrot_ec_init(void);</span><br><span> u8 parrot_rev(void);</span><br><span> int parrot_ec_running_ro(void);</span><br><span>diff --git a/src/mainboard/roda/rk886ex/m3885.h b/src/mainboard/roda/rk886ex/m3885.h</span><br><span>index d2dcb14..1f93d1e 100644</span><br><span>--- a/src/mainboard/roda/rk886ex/m3885.h</span><br><span>+++ b/src/mainboard/roda/rk886ex/m3885.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _MAINBOARD_M3885_H</span><br><span> #define _MAINBOARD_M3885_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define M3885_CMCMD 0x04</span><br><span> #define M3885_CMDAT1 0x05</span><br><span> #define M3885_CMDAT2 0x06</span><br><span>diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h</span><br><span>index e80edc5..48e6af4 100644</span><br><span>--- a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h</span><br><span>+++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h</span><br><span>@@ -13,6 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const u32 cim_verb_data[] = {</span><br><span> /* coreboot specific header */</span><br><span> 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */</span><br><span>diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h</span><br><span>index edc5f64..ec4e4fc 100644</span><br><span>--- a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h</span><br><span>+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h</span><br><span>@@ -13,6 +13,8 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const u32 cim_verb_data[] = {</span><br><span> /* coreboot specific header */</span><br><span> 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.h b/src/mainboard/siemens/mc_tcu3/lcd_panel.h</span><br><span>index a27cc52..377a066 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/lcd_panel.h</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _LCD_PANEL_H_</span><br><span> #define _LCD_PANEL_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* This GPIOs are used for LCD panel type encoding */</span><br><span> #define LCD_TYPE_GPIO_BIT0 40</span><br><span> #define LCD_TYPE_GPIO_BIT1 41</span><br><span>diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h</span><br><span>index 211ee24..e9a13ea 100644</span><br><span>--- a/src/northbridge/amd/agesa/family14/chip.h</span><br><span>+++ b/src/northbridge/amd/agesa/family14/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _NB_AGESA_CHIP_H_</span><br><span> #define _NB_AGESA_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_agesa_family14_config</span><br><span> {</span><br><span> /*</span><br><span>diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h</span><br><span>index a520708..1df2d82 100644</span><br><span>--- a/src/northbridge/amd/agesa/family15tn/chip.h</span><br><span>+++ b/src/northbridge/amd/agesa/family15tn/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _NB_AGESA_CHIP_H_</span><br><span> #define _NB_AGESA_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_agesa_family15tn_config</span><br><span> {</span><br><span> u8 spdAddrLookup[2][2][4];</span><br><span>diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h</span><br><span>index 37b5cc1..1fed152 100644</span><br><span>--- a/src/northbridge/amd/agesa/family16kb/chip.h</span><br><span>+++ b/src/northbridge/amd/agesa/family16kb/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _NB_AGESA_CHIP_H_</span><br><span> #define _NB_AGESA_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_agesa_family16kb_config</span><br><span> {</span><br><span> u8 spdAddrLookup[2][2][4];</span><br><span>diff --git a/src/northbridge/amd/amdfam10/northbridge.h b/src/northbridge/amd/amdfam10/northbridge.h</span><br><span>index 69d7415..349becb 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/northbridge.h</span><br><span>+++ b/src/northbridge/amd/amdfam10/northbridge.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef NORTHBRIDGE_AMD_AMDFAM10_H</span><br><span> #define NORTHBRIDGE_AMD_AMDFAM10_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> u32 amdfam10_scan_root_bus(struct device *root, u32 max);</span><br><span> void get_pci1234(void);</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdht/AsPsNb.h b/src/northbridge/amd/amdht/AsPsNb.h</span><br><span>index 3500892..b90598d 100644</span><br><span>--- a/src/northbridge/amd/amdht/AsPsNb.h</span><br><span>+++ b/src/northbridge/amd/amdht/AsPsNb.h</span><br><span>@@ -13,10 +13,11 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #ifndef ASPSNB_H</span><br><span> #define ASPSNB_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> u8 getMinNbCOF(void);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/northbridge/amd/pi/00630F01/chip.h b/src/northbridge/amd/pi/00630F01/chip.h</span><br><span>index 35b4a57..3032c30 100644</span><br><span>--- a/src/northbridge/amd/pi/00630F01/chip.h</span><br><span>+++ b/src/northbridge/amd/pi/00630F01/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _AGESA_00630F01_CHIP_H_</span><br><span> #define _AGESA_00630F01_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_pi_00630F01_config</span><br><span> {</span><br><span> u8 spdAddrLookup[1][2][2];</span><br><span>diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h</span><br><span>index ab0e3d2..f9614ca 100644</span><br><span>--- a/src/northbridge/amd/pi/00660F01/chip.h</span><br><span>+++ b/src/northbridge/amd/pi/00660F01/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _PI_FAM15CZ_CHIP_H_</span><br><span> #define _PI_FAM15CZ_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_pi_00660F01_config</span><br><span> {</span><br><span> u8 spdAddrLookup[2][2][4];</span><br><span>diff --git a/src/northbridge/amd/pi/00730F01/chip.h b/src/northbridge/amd/pi/00730F01/chip.h</span><br><span>index 3db79d4..99754eb 100644</span><br><span>--- a/src/northbridge/amd/pi/00730F01/chip.h</span><br><span>+++ b/src/northbridge/amd/pi/00730F01/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef _PI_00730F01_CHIP_H_</span><br><span> #define _PI_00730F01_CHIP_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct northbridge_amd_pi_00730F01_config</span><br><span> {</span><br><span> u8 spdAddrLookup[1][1][2];</span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h</span><br><span>index dc8de74..60133f4 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.h</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef PINEVIEW_RAMINIT_H</span><br><span> #define PINEVIEW_RAMINIT_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void sdram_initialize(int boot_path, const u8 *sdram_addresses);</span><br><span> </span><br><span> #endif /* PINEVIEW_RAMINIT_H */</span><br><span>diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h</span><br><span>index db608c5..debb1aa 100644</span><br><span>--- a/src/northbridge/intel/x4x/iomap.h</span><br><span>+++ b/src/northbridge/intel/x4x/iomap.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef X4X_IOMAP_H</span><br><span> #define X4X_IOMAP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* 4 KB per PCIe device */</span><br><span> #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS</span><br><span> </span><br><span>diff --git a/src/soc/cavium/common/pci/chip.h b/src/soc/cavium/common/pci/chip.h</span><br><span>index 0d0d33f..ccc1551 100644</span><br><span>--- a/src/soc/cavium/common/pci/chip.h</span><br><span>+++ b/src/soc/cavium/common/pci/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __SOC_CAVIUM_COMMON_PCI_CHIP_H</span><br><span> #define __SOC_CAVIUM_COMMON_PCI_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_cavium_common_pci_config {</span><br><span> /**</span><br><span> * Mark the PCI device as secure.</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>index 33e4c2d..4e172f3 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/xhci.h</span><br><span>@@ -51,6 +51,7 @@</span><br><span> #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span> void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/display.h b/src/soc/nvidia/tegra210/include/soc/display.h</span><br><span>index 74c289e..86750c9 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/display.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/display.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__</span><br><span> #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define COLOR_WHITE 0xFFFFFF</span><br><span> #define COLOR_BLACK 0x000000</span><br><span> </span><br><span>diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>index dbaaa22..245385f 100644</span><br><span>--- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>+++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h</span><br><span>@@ -15,6 +15,8 @@</span><br><span> #ifndef __TEGRA_DSI_H__</span><br><span> #define __TEGRA_DSI_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define DSI_INCR_SYNCPT 0x00</span><br><span> #define DSI_INCR_SYNCPT_CONTROL 0x01</span><br><span> #define DSI_INCR_SYNCPT_ERROR 0x02</span><br><span>diff --git a/src/soc/rockchip/common/include/soc/pwm.h b/src/soc/rockchip/common/include/soc/pwm.h</span><br><span>index 4b4b2c0..90f077c 100644</span><br><span>--- a/src/soc/rockchip/common/include/soc/pwm.h</span><br><span>+++ b/src/soc/rockchip/common/include/soc/pwm.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H</span><br><span> #define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void pwm_init(u32 id, u32 period_ns, u32 duty_ns);</span><br><span> </span><br><span> #endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H */</span><br><span>diff --git a/src/soc/rockchip/rk3288/include/soc/display.h b/src/soc/rockchip/rk3288/include/soc/display.h</span><br><span>index 8ffa922..cc76629 100644</span><br><span>--- a/src/soc/rockchip/rk3288/include/soc/display.h</span><br><span>+++ b/src/soc/rockchip/rk3288/include/soc/display.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef __SOC_ROCKCHIP_RK3288_DISPLAY_H__</span><br><span> #define __SOC_ROCKCHIP_RK3288_DISPLAY_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * this bit select edp phy pll, this bit define different between</span><br><span> * rk3288 and rk3399 in edp phy, so implement it in soc specific code</span><br><span>diff --git a/src/soc/rockchip/rk3399/include/soc/saradc.h b/src/soc/rockchip/rk3399/include/soc/saradc.h</span><br><span>index 90f743e..69118b5 100644</span><br><span>--- a/src/soc/rockchip/rk3399/include/soc/saradc.h</span><br><span>+++ b/src/soc/rockchip/rk3399/include/soc/saradc.h</span><br><span>@@ -17,5 +17,7 @@</span><br><span> #ifndef __SOC_ROCKCHIP_RK3399_SARADC_H__</span><br><span> #define __SOC_ROCKCHIP_RK3399_SARADC_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> u32 get_saradc_value(u32 chn);</span><br><span> #endif</span><br><span>diff --git a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>index 0833934..635a9bb 100644</span><br><span>--- a/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>+++ b/src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H</span><br><span> #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* These are pointers to function pointers. Double indirection! */</span><br><span> static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;</span><br><span> static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;</span><br><span>diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>index 40af40b..2c8cef0 100644</span><br><span>--- a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>+++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H</span><br><span> #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* These are pointers to function pointers. Double indirection! */</span><br><span> static void **const irom_sdmmc_read_blocks_ptr = (void **)0x02020030;</span><br><span> static void **const irom_msh_read_from_fifo_emmc_ptr = (void **)0x02020044;</span><br><span>diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h</span><br><span>index 873d7fb..27d6dfb 100644</span><br><span>--- a/src/southbridge/amd/agesa/hudson/chip.h</span><br><span>+++ b/src/southbridge/amd/agesa/hudson/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef HUDSON_CHIP_H</span><br><span> #define HUDSON_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_amd_agesa_hudson_config</span><br><span> {</span><br><span> u8 sd_mode;</span><br><span>diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h</span><br><span>index 16ac6fe..70b3e4f 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef _CIMX_H_</span><br><span> #define _CIMX_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /**</span><br><span> * AMD South Bridge CIMx entry point wrapper</span><br><span> */</span><br><span>diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h</span><br><span>index 99b246e..1746050 100644</span><br><span>--- a/src/southbridge/amd/cimx/sb900/sb_cimx.h</span><br><span>+++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef _CIMX_SB_EARLY_H_</span><br><span> #define _CIMX_SB_EARLY_H_</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PM_INDEX 0xcd6</span><br><span> #define PM_DATA 0xcd7</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb700/chip.h b/src/southbridge/amd/sb700/chip.h</span><br><span>index fe3289d..13ff48a 100644</span><br><span>--- a/src/southbridge/amd/sb700/chip.h</span><br><span>+++ b/src/southbridge/amd/sb700/chip.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SB700_CHIP_H</span><br><span> #define SB700_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct southbridge_amd_sb700_config</span><br><span> {</span><br><span> u32 boot_switch_sata_ide : 1;</span><br><span>diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h</span><br><span>index 7bf47f3..7153798 100644</span><br><span>--- a/src/southbridge/intel/common/pciehp.h</span><br><span>+++ b/src/southbridge/intel/common/pciehp.h</span><br><span>@@ -1,2 +1,9 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOUTHBRIDGE_INTEL_COMMON_PCIEPH_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOUTHBRIDGE_INTEL_COMMON_PCIEPH_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);</span><br><span> void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h</span><br><span>index ec54165..8da1379 100644</span><br><span>--- a/src/superio/fintek/f81216h/f81216h.h</span><br><span>+++ b/src/superio/fintek/f81216h/f81216h.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SUPERIO_FINTEK_F81216H_H</span><br><span> #define SUPERIO_FINTEK_F81216H_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Logical Device Numbers (LDN). */</span><br><span> #define F81216H_SP1 0x00 /* UART1 (+CIR mode) */</span><br><span> #define F81216H_SP2 0x01 /* UART2 */</span><br><span>diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h</span><br><span>index d351053..a35fb3c 100644</span><br><span>--- a/src/superio/nuvoton/nct5104d/chip.h</span><br><span>+++ b/src/superio/nuvoton/nct5104d/chip.h</span><br><span>@@ -17,6 +17,8 @@</span><br><span> #ifndef SUPERIO_NUVOTON_NCT5104D_CHIP_H</span><br><span> #define SUPERIO_NUVOTON_NCT5104D_CHIP_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct superio_nuvoton_nct5104d_config {</span><br><span> u8 irq_trigger_type;</span><br><span> };</span><br><span>diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h</span><br><span>index ab9b9c8..c3dfd02 100644</span><br><span>--- a/src/superio/serverengines/pilot/pilot.h</span><br><span>+++ b/src/superio/serverengines/pilot/pilot.h</span><br><span>@@ -18,6 +18,8 @@</span><br><span> #ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H</span><br><span> #define SUPERIO_SERVERENGINES_PILOT_PILOT_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* PILOT Super I/O is only based on LPC observation done on factory system. */</span><br><span> </span><br><span> #define PILOT_LD1 0x01 /* Logical device 1 */</span><br><span>diff --git a/src/superio/smsc/lpc47n227/lpc47n227.h b/src/superio/smsc/lpc47n227/lpc47n227.h</span><br><span>index d629a67..8d958f1 100644</span><br><span>--- a/src/superio/smsc/lpc47n227/lpc47n227.h</span><br><span>+++ b/src/superio/smsc/lpc47n227/lpc47n227.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef SUPERIO_SMSC_LPC47N227_LPC47N227_H</span><br><span> #define SUPERIO_SMSC_LPC47N227_LPC47N227_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Since the LPC47N227 does not have logical devices but a flat configuration</span><br><span> * space, these are arbitrary, but must match declarations in the mainboard</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29403">change 29403</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29403"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 </div>
<div style="display:none"> Gerrit-Change-Number: 29403 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>