[coreboot-gerrit] Change in coreboot[master]: cpu/amd: Replace MSR addresses with macros
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Wed Oct 31 08:07:30 CET 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29369
Change subject: cpu/amd: Replace MSR addresses with macros
......................................................................
cpu/amd: Replace MSR addresses with macros
Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/amd/car/cache_as_ram.inc
M src/cpu/amd/microcode/microcode.c
M src/include/cpu/amd/msr.h
3 files changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29369/1
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7cbf1db..e4c2704 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -415,26 +415,26 @@
jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */
- mov $0xc0011020, %ecx
+ mov $LS_CFG_MSR, %ecx
rdmsr
bts $28, %eax
wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
- mov $0xc0011021, %ecx
+ mov $IC_CFG_MSR, %ecx
rdmsr
bts $9, %eax
wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
- mov $0xc0011022, %ecx
+ mov $DC_CFG_MSR, %ecx
rdmsr
bts $4, %eax
bts $13, %eax
wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */
- mov $0xc001102b, %ecx
+ mov $BU_CFG3_MSR, %ecx
rdmsr
btr $49-32, %edx
wrmsr
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 68b6953..dad040b 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -121,7 +121,7 @@
msr.hi = 0;
msr.lo = (uint32_t)m;
- wrmsr(0xc0010020, msr);
+ wrmsr(MSR_PATCH_LOADER, msr);
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 46ec70d..5d7b5e4 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -58,6 +58,8 @@
#define PSTATE_3_MSR 0xC0010067
#define PSTATE_4_MSR 0xC0010068
+#define MSR_PATCH_LOADER 0xC0010020
+
#define MSR_COFVID_STS 0xC0010071
#define MSR_CSTATE_ADDRESS 0xC0010073
#define OSVW_ID_Length 0xC0010140
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c
Gerrit-Change-Number: 29369
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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