<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29369">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/amd: Replace MSR addresses with macros<br><br>Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/car/cache_as_ram.inc<br>M src/cpu/amd/microcode/microcode.c<br>M src/include/cpu/amd/msr.h<br>3 files changed, 7 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29369/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc</span><br><span>index 7cbf1db..e4c2704 100644</span><br><span>--- a/src/cpu/amd/car/cache_as_ram.inc</span><br><span>+++ b/src/cpu/amd/car/cache_as_ram.inc</span><br><span>@@ -415,26 +415,26 @@</span><br><span> </span><br><span> jmp_if_not_fam15h(fam15_car_msr_setup_complete)</span><br><span> /* Disable streaming store (DisSS = 1) */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $0xc0011020, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $LS_CFG_MSR, %ecx</span><br><span> rdmsr</span><br><span> bts $28, %eax</span><br><span> wrmsr</span><br><span> </span><br><span> /* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $0xc0011021, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $IC_CFG_MSR, %ecx</span><br><span> rdmsr</span><br><span> bts $9, %eax</span><br><span> wrmsr</span><br><span> </span><br><span> /* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $0xc0011022, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $DC_CFG_MSR, %ecx</span><br><span> rdmsr</span><br><span> bts $4, %eax</span><br><span> bts $13, %eax</span><br><span> wrmsr</span><br><span> </span><br><span> /* Disable CR0 combining (CombineCr0Cd = 0) */</span><br><span style="color: hsl(0, 100%, 40%);">- mov $0xc001102b, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $BU_CFG3_MSR, %ecx</span><br><span> rdmsr</span><br><span> btr $49-32, %edx</span><br><span> wrmsr</span><br><span>diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c</span><br><span>index 68b6953..dad040b 100644</span><br><span>--- a/src/cpu/amd/microcode/microcode.c</span><br><span>+++ b/src/cpu/amd/microcode/microcode.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> msr.hi = 0;</span><br><span> msr.lo = (uint32_t)m;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(0xc0010020, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PATCH_LOADER, msr);</span><br><span> </span><br><span> UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);</span><br><span> </span><br><span>diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h</span><br><span>index 46ec70d..5d7b5e4 100644</span><br><span>--- a/src/include/cpu/amd/msr.h</span><br><span>+++ b/src/include/cpu/amd/msr.h</span><br><span>@@ -58,6 +58,8 @@</span><br><span> #define PSTATE_3_MSR 0xC0010067</span><br><span> #define PSTATE_4_MSR 0xC0010068</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PATCH_LOADER 0xC0010020</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define MSR_COFVID_STS 0xC0010071</span><br><span> #define MSR_CSTATE_ADDRESS 0xC0010073</span><br><span> #define OSVW_ID_Length 0xC0010140</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29369">change 29369</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29369"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c </div>
<div style="display:none"> Gerrit-Change-Number: 29369 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>