[coreboot-gerrit] Change in coreboot[master]: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the...

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/29339


Change subject: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode
......................................................................

src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode

Pointer to opcode increases by unit uint16_t not byte.

Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5
Signed-off-by: Philipp Hug <philipp at hug.cx>
---
M src/arch/riscv/misaligned.c
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29339/1

diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index ba96102..ebff2d6 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -160,7 +160,7 @@
 static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
 {
 	uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0);
-	uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 2);
+	uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1);
 	uint32_t ins = (h << 16) | l;
 	if ((EXTRACT_FIELD(ins, 0x3) == 3) &&
 		(EXTRACT_FIELD(ins, 0x1c) != 0x7)) {

-- 
To view, visit https://review.coreboot.org/29339
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5
Gerrit-Change-Number: 29339
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181029/ff9235b2/attachment.html>