[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29333


Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area
......................................................................

src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area

Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks at eltan.com>
---
M src/soc/intel/braswell/northcluster.c
1 file changed, 13 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29333/1

diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 88f7d0c..0554cd3 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -93,6 +94,7 @@
 	unsigned long fsp_res_base_k;
 	unsigned long base_k, size_k;
 	const unsigned long four_gig_kib = (4 << (30 - 10));
+	void *fsp_reserved_memory_area;
 	int index = 0;
 
 	/* Read standard PCI resources. */
@@ -104,7 +106,15 @@
 	tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);
 
 	/* Determine the base of the FSP reserved memory */
-	fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top());
+	fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
+	if (fsp_reserved_memory_area){
+		fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area));
+	}
+	else
+	{
+		/* If no FSP reserverd area */
+		fsp_res_base_k = tseg_base_k;
+	}
 
 	/* PCIe memory-mapped config space access - 256 MiB. */
 	mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
@@ -115,8 +125,8 @@
 	size_k = RES_IN_KIB(0xa0000) - base_k;
 	ram_resource(dev, index++, base_k, size_k);
 
-	/* 0xc0000 -> fsp_res_base - cacheable and usable */
-	base_k = RES_IN_KIB(0xc0000);
+	/* High memory -> fsp_res_base - cacheable and usable */
+	base_k = RES_IN_KIB(0x100000);
 	size_k = fsp_res_base_k - base_k;
 	ram_resource(dev, index++, base_k, size_k);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Gerrit-Change-Number: 29333
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
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