<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29333">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area<br><br>Calculation of memory reserved by FSP is incorrect.<br>Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area<br><br>BUG=N/A<br>TEST=Intel CherryHill CRB<br><br>Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/soc/intel/braswell/northcluster.c<br>1 file changed, 13 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29333/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c</span><br><span>index 88f7d0c..0554cd3 100644</span><br><span>--- a/src/soc/intel/braswell/northcluster.c</span><br><span>+++ b/src/soc/intel/braswell/northcluster.c</span><br><span>@@ -3,6 +3,7 @@</span><br><span>  *</span><br><span>  * Copyright (C) 2013 Google Inc.</span><br><span>  * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -93,6 +94,7 @@</span><br><span>     unsigned long fsp_res_base_k;</span><br><span>        unsigned long base_k, size_k;</span><br><span>        const unsigned long four_gig_kib = (4 << (30 - 10));</span><br><span style="color: hsl(120, 100%, 40%);">+    void *fsp_reserved_memory_area;</span><br><span>      int index = 0;</span><br><span> </span><br><span>   /* Read standard PCI resources. */</span><br><span>@@ -104,7 +106,15 @@</span><br><span>    tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);</span><br><span> </span><br><span>         /* Determine the base of the FSP reserved memory */</span><br><span style="color: hsl(0, 100%, 40%);">-     fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top());</span><br><span style="color: hsl(120, 100%, 40%);">+     fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);</span><br><span style="color: hsl(120, 100%, 40%);">+  if (fsp_reserved_memory_area){</span><br><span style="color: hsl(120, 100%, 40%);">+                fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area));</span><br><span style="color: hsl(120, 100%, 40%);">+        }</span><br><span style="color: hsl(120, 100%, 40%);">+     else</span><br><span style="color: hsl(120, 100%, 40%);">+  {</span><br><span style="color: hsl(120, 100%, 40%);">+             /* If no FSP reserverd area */</span><br><span style="color: hsl(120, 100%, 40%);">+                fsp_res_base_k = tseg_base_k;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span>        /* PCIe memory-mapped config space access - 256 MiB. */</span><br><span>      mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);</span><br><span>@@ -115,8 +125,8 @@</span><br><span>       size_k = RES_IN_KIB(0xa0000) - base_k;</span><br><span>       ram_resource(dev, index++, base_k, size_k);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* 0xc0000 -> fsp_res_base - cacheable and usable */</span><br><span style="color: hsl(0, 100%, 40%);">- base_k = RES_IN_KIB(0xc0000);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* High memory -> fsp_res_base - cacheable and usable */</span><br><span style="color: hsl(120, 100%, 40%);">+   base_k = RES_IN_KIB(0x100000);</span><br><span>       size_k = fsp_res_base_k - base_k;</span><br><span>    ram_resource(dev, index++, base_k, size_k);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29333">change 29333</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29333"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b </div>
<div style="display:none"> Gerrit-Change-Number: 29333 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>