[coreboot-gerrit] Change in coreboot[master]: mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/29316


Change subject: mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6
......................................................................

mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6

Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/mainboard/intel/icelake_rvp/chromeos.fmd
1 file changed, 17 insertions(+), 18 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29316/1

diff --git a/src/mainboard/intel/icelake_rvp/chromeos.fmd b/src/mainboard/intel/icelake_rvp/chromeos.fmd
index 65d22c3..b4dd69b 100644
--- a/src/mainboard/intel/icelake_rvp/chromeos.fmd
+++ b/src/mainboard/intel/icelake_rvp/chromeos.fmd
@@ -1,21 +1,21 @@
 FLASH at 0xff000000 0x1000000 {
-	SI_ALL at 0x0 0x380000 {
+	SI_ALL at 0x0 0x3F0000 {
 		SI_DESC at 0x0 0x1000
-		SI_EC at 0x01000 0x80000
-		SI_ME at 0x81000 0x2ff000
+		SI_EC at 0x1000 0x80000
+		SI_ME at 0x81000 0x36F000
 	}
-	SI_BIOS at 0x380000 0xc80000 {
-		RW_SECTION_A at 0x0 0x368000 {
+	SI_BIOS at 0x400000 0xC00000 {
+		RW_SECTION_A at 0x0 0x2d0000 {
 			VBLOCK_A at 0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x357fc0
-			RW_FWID_A at 0x367fc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A at 0x2cffc0 0x40
 		}
-		RW_SECTION_B at 0x368000 0x368000 {
+		RW_SECTION_B at 0x2d0000 0x2d0000 {
 			VBLOCK_B at 0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x357fc0
-			RW_FWID_B at 0x367fc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B at 0x2cffc0 0x40
 		}
-		RW_MISC at 0x6d0000 0x30000 {
+		RW_MISC at 0x5a0000 0x30000 {
 			UNIFIED_MRC_CACHE at 0x0 0x20000 {
 				RECOVERY_MRC_CACHE at 0x0 0x10000
 				RW_MRC_CACHE at 0x10000 0x10000
@@ -28,18 +28,17 @@
 			RW_VPD at 0x28000 0x2000
 			RW_NVRAM at 0x2a000 0x6000
 		}
-		SMMSTORE at 0x700000 0x40000
-		RW_LEGACY(CBFS)@0x740000 0x1c0000
-		WP_RO at 0x900000 0x380000 {
+		SMMSTORE at 0x5d0000 0x40000
+		RW_LEGACY(CBFS)@0x610000 0x1c0000
+		WP_RO at 0x7d0000 0x430000 {
 			RO_VPD at 0x0 0x4000
-			RO_UNUSED at 0x4000 0xc000
-			RO_SECTION at 0x10000 0x370000 {
+			RO_SECTION at 0x4000 0x42c000 {
 				FMAP at 0x0 0x800
 				RO_FRID at 0x800 0x40
 				RO_FRID_PAD at 0x840 0x7c0
 				GBB at 0x1000 0xef000
-				COREBOOT(CBFS)@0xf0000 0x280000
+				COREBOOT(CBFS)@0xf0000 0x33c000
 			}
 		}
 	}
-}
+}
\ No newline at end of file

-- 
To view, visit https://review.coreboot.org/29316
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Gerrit-Change-Number: 29316
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181029/db82aaa1/attachment.html>