[coreboot-gerrit] Change in coreboot[master]: src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/29255


Change subject: src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2
......................................................................

src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2

This change allows to redirect coreboot console output to COM2 by
setting appropriate UART index in Console menu in Kconfig.

Change is helpful for users which would like to use COM1 port for
other purposes, because COM1 is the only port with hardware flow
control.

Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f
Signed-off-by: Michał Żygowski <michal.zygowski at 3mdeb.com>
---
M src/mainboard/pcengines/apu2/romstage.c
1 file changed, 23 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29255/1

diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index fec25b4..afa01d8 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -19,6 +19,7 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <arch/stages.h>
+#include <device/pnp.h>
 #include <device/pnp_def.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
@@ -32,10 +33,16 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct5104d/nct5104d.h>
 #include <Fch/Fch.h>
 
 #include "gpio_ftns.h"
 
+#define SIO_PORT 0x2e
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
+
 static void early_lpc_init(void);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -56,6 +63,9 @@
 	hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
+		pci_devfn_t dev;
+		u32 data;
+
 		timestamp_init(timestamp_get());
 		timestamp_add_now(TS_START_ROMSTAGE);
 
@@ -64,6 +74,19 @@
 
 		hudson_clk_output_48Mhz();
 		post_code(0x31);
+
+		dev = PCI_DEV(0, 0x14, 3);
+		data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+		/* enable 0x2e/0x4e IO decoding before configuring SuperIO */
+		pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
+
+		/* COM2 on apu5 is reserved so only COM1 should be supported */
+		if ((CONFIG_UART_FOR_CONSOLE == 1) &&
+			 !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+			nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+		else if (CONFIG_UART_FOR_CONSOLE == 0)
+			nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
+
 		console_init();
 	}
 

-- 
To view, visit https://review.coreboot.org/29255
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f
Gerrit-Change-Number: 29255
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181024/3e15350e/attachment.html>