<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29255">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2<br><br>This change allows to redirect coreboot console output to COM2 by<br>setting appropriate UART index in Console menu in Kconfig.<br><br>Change is helpful for users which would like to use COM1 port for<br>other purposes, because COM1 is the only port with hardware flow<br>control.<br><br>Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/mainboard/pcengines/apu2/romstage.c<br>1 file changed, 23 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29255/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>index fec25b4..afa01d8 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <arch/io.h></span><br><span> #include <arch/stages.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp.h></span><br><span> #include <device/pnp_def.h></span><br><span> #include <arch/cpu.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span>@@ -32,10 +33,16 @@</span><br><span> #include <cpu/x86/bist.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <southbridge/amd/pi/hudson/hudson.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct5104d/nct5104d.h></span><br><span> #include <Fch/Fch.h></span><br><span> </span><br><span> #include "gpio_ftns.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_PORT 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void early_lpc_init(void);</span><br><span> </span><br><span> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)</span><br><span>@@ -56,6 +63,9 @@</span><br><span> hudson_lpc_port80();</span><br><span> </span><br><span> if (!cpu_init_detectedx && boot_cpu()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 data;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> timestamp_init(timestamp_get());</span><br><span> timestamp_add_now(TS_START_ROMSTAGE);</span><br><span> </span><br><span>@@ -64,6 +74,19 @@</span><br><span> </span><br><span> hudson_clk_output_48Mhz();</span><br><span> post_code(0x31);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCI_DEV(0, 0x14, 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable 0x2e/0x4e IO decoding before configuring SuperIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* COM2 on apu5 is reserved so only COM1 should be supported */</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((CONFIG_UART_FOR_CONSOLE == 1) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (CONFIG_UART_FOR_CONSOLE == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> console_init();</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29255">change 29255</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f </div>
<div style="display:none"> Gerrit-Change-Number: 29255 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>