[coreboot-gerrit] Change in coreboot[master]: Nami: Add field to identify single channel DDR
Shelley Chen (Code Review)
gerrit at coreboot.org
Tue Oct 23 03:33:01 CEST 2018
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/29233
Change subject: Nami: Add field to identify single channel DDR
......................................................................
Nami: Add field to identify single channel DDR
Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen at google.com>
---
M src/mainboard/google/poppy/romstage.c
M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/poppy/variants/nami/gpio.c
M src/mainboard/google/poppy/variants/nami/mainboard.c
4 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29233/1
diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c
index f49fbf4..c77fdf0 100644
--- a/src/mainboard/google/poppy/romstage.c
+++ b/src/mainboard/google/poppy/romstage.c
@@ -163,6 +163,9 @@
memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size);
mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd);
- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+ if (p.single_channel)
+ mem_cfg->MemorySpdPtr10 = 0;
+ else
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
mem_cfg->MemorySpdDataLen = spd_info[p.type].len;
}
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
index 7e850b6..7851c31 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
@@ -48,6 +48,9 @@
const void *rcomp_target;
size_t rcomp_target_size;
bool use_sec_spd;
+
+ /* This would be set to true if only have single DDR channel */
+ bool single_channel;
};
void variant_memory_params(struct memory_params *p);
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 2d0fea4..8f10f12 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -179,8 +179,8 @@
PAD_CFG_NC(GPP_D8),
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),
- /* D10 : ISH_SPI_CLK ==> SPKR_RST_L (unstuffed) */
- PAD_CFG_NC(GPP_D10),
+ /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP),
/* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */
PAD_CFG_NC(GPP_D11),
/* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */
@@ -370,6 +370,9 @@
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
+
+ /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c
index 2052ae0..c7424ad 100644
--- a/src/mainboard/google/poppy/variants/nami/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nami/mainboard.c
@@ -254,5 +254,10 @@
sku_overwrite_mapping[oem_index].ac_loadline[i];
cfg->domain_vr_config[i].dc_loadline =
sku_overwrite_mapping[oem_index].dc_loadline[i];
+
}
+
+ /* GPP_D10 set to 0 for dual channel and 1 for single channel */
+ if (gpio_get(GPP_D10))
+ p->single_channel = 1;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Gerrit-Change-Number: 29233
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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