[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Remove dev_find_slot where possible
Richard Spiegel (Code Review)
gerrit at coreboot.org
Mon Oct 22 22:57:32 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29227
Change subject: soc/amd/stoneyridge: Remove dev_find_slot where possible
......................................................................
soc/amd/stoneyridge: Remove dev_find_slot where possible
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/lpc.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/southbridge.c
5 files changed, 25 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29227/1
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 92b2950..3741703 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -55,8 +55,8 @@
static int get_cpu_count(void)
{
- struct device *nb = dev_find_slot(0, HT_DEVFN);
- return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1;
+ return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK)
+ + 1;
}
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 27e1f70..78bed2a 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -98,6 +98,7 @@
/* D18F5 */
#define nb_capabilities2 0x84
#define cmp_cap_mask 0xff
+
enum {
/* SMM handler area. */
SMM_SUBREGION_HANDLER,
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index 6833db6..317574b 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -38,32 +38,30 @@
{
u8 byte;
u32 dword;
- struct device *sm_dev;
/*
* Enable the LPC Controller
* SMBus register 0x64 is not defined in public datasheet.
*/
- sm_dev = dev_find_slot(0, SMBUS_DEVFN);
- dword = pci_read_config32(sm_dev, 0x64);
+ dword = pci_read_config32(SOC_SMBUS_DEV, 0x64);
dword |= 1 << 20;
- pci_write_config32(sm_dev, 0x64, dword);
+ pci_write_config32(SOC_SMBUS_DEV, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* Enable DMA transaction on the LPC bus */
- byte = pci_read_config8(dev, LPC_PCI_CONTROL);
+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL);
byte |= LEGACY_DMA_EN;
- pci_write_config8(dev, LPC_PCI_CONTROL, byte);
+ pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte);
/* Disable the timeout mechanism on LPC */
- byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;
- pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
+ pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
/* Disable LPC MSI Capability */
- byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);
+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS);
/* BIT 1 is not defined in public datasheet. */
byte &= ~(1 << 1);
@@ -73,15 +71,15 @@
* interrupt and visit LPC.
*/
byte &= ~LPC_NOHOG;
- pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
+ pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte);
/*
* Enable hand-instance of the pulse generator and SPI
* controller prefetch of flash.
*/
- byte = pci_read_config8(dev, LPC_HOST_CONTROL);
+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL);
byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
- pci_write_config8(dev, LPC_HOST_CONTROL, byte);
+ pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte);
cmos_check_update_date();
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 4e844af..d17d855 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -47,27 +47,25 @@
u32 io_min, u32 io_max)
{
u32 tempreg;
- struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
| ((io_max & 0xf0) << (12 - 4));
- pci_write_config32(addr_map, reg + 4, tempreg);
+ pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */
- pci_write_config32(addr_map, reg, tempreg);
+ pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
}
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 mmio_min, u32 mmio_max)
{
u32 tempreg;
- struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
- pci_write_config32(addr_map, reg + 4, tempreg);
+ pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
- pci_write_config32(addr_map, reg, tempreg);
+ pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
}
static void read_resources(struct device *dev)
@@ -153,8 +151,7 @@
printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
/* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
- pci_write_config32(dev_find_slot(0, ADDR_DEVFN),
- D18F1_VGAEN, VGA_ADDR_ENABLE);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
}
static void set_resources(struct device *dev)
@@ -379,17 +376,16 @@
void fam15_finalize(void *chip_info)
{
- struct device *dev;
u32 value;
- dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
- pci_write_config32(dev, NB_IOAPIC_INDEX, 0);
- pci_write_config32(dev, NB_IOAPIC_DATA, 5); /* TODO: move to dsdt.asl */
+
+ /* TODO: move IOAPIC code to dsdt.asl */
+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);
+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);
/* disable No Snoop */
- dev = dev_find_slot(0, HDA0_DEVFN);
- value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS);
+ value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
value &= ~HDA_NO_SNOOP_EN;
- pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);
+ pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
}
static void reserve_domain_res(unsigned int start, unsigned int end)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b188b76..6a94b4c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -892,7 +892,7 @@
uintptr_t xhci_fw;
uintptr_t fwaddr;
size_t fwsize;
- const struct device *sd, *sata, *ehci;
+ const struct device *sd, *sata;
struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs == NULL)
@@ -925,7 +925,6 @@
gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
gnvs->fw03 = fwsize << 16;
- ehci = dev_find_slot(0, EHCI1_DEVFN);
gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Gerrit-Change-Number: 29227
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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